| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 01/27/1999 | EP0893799A2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
| 01/27/1999 | EP0892988A1 Integrated circuit protection device and method |
| 01/27/1999 | EP0892972A1 High-speed video frame buffer using single port memory chips where pixel intensity values for display regions are stored at consecutive addresses of memory blocks |
| 01/27/1999 | CN1206489A Memory |
| 01/27/1999 | CN1206198A Apparatus for controlling circuit response during power-up |
| 01/27/1999 | CN1206196A Data determining circuitry and data determining method |
| 01/26/1999 | US5864872 Single wire communication system |
| 01/26/1999 | US5864801 Methods of efficiently recording and reproducing an audio signal in a memory using hierarchical encoding |
| 01/26/1999 | US5864696 Circuit and method for setting the time duration of a write to a memory cell |
| 01/26/1999 | US5864568 Semiconductor memory device for mass storage block access applications |
| 01/26/1999 | US5864567 Data memory apparatus |
| 01/26/1999 | US5864512 High-speed video frame buffer using single port memory chips |
| 01/26/1999 | US5864511 Semiconductor memory device using cross-coupled load and precharge circuit for bit line pairs |
| 01/26/1999 | US5864509 Method and apparatus for reducing continuous write cycle current in memory device |
| 01/26/1999 | US5864506 Memory having selectable output strength |
| 01/26/1999 | US5864505 Random access memory with plural simultaneously operable banks |
| 01/26/1999 | US5864504 Voltage generating circuit |
| 01/26/1999 | US5864502 Sensing circuit for EEPROM |
| 01/26/1999 | US5864497 Memory device having divided global bit lines |
| 01/26/1999 | US5864496 High density semiconductor memory having diagonal bit lines and dual word lines |
| 01/21/1999 | WO1999003106A1 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
| 01/21/1999 | DE19741426C1 Data storage circuit |
| 01/20/1999 | EP0892409A2 Semiconductor memory device |
| 01/20/1999 | EP0892355A1 Method and system for committing modifications to hierarchically structured data |
| 01/20/1999 | CN1205523A Read only memory |
| 01/19/1999 | US5862396 Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system |
| 01/19/1999 | US5862099 Non-volatile programmable memory having a buffering capability and method of operation thereof |
| 01/19/1999 | US5862097 Semiconductor memory device |
| 01/19/1999 | US5862095 Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system |
| 01/19/1999 | US5862093 Dynamic memory device with circuits for setting self-refreshing period |
| 01/19/1999 | US5862090 Semiconductor memory device having cell array divided into a plurality of cell blocks |
| 01/19/1999 | US5862089 Method and memory device for dynamic cell plate sensing with ac equilibrate |
| 01/19/1999 | US5862084 Semiconductor memory device |
| 01/19/1999 | US5862077 Fast sensing amplifier for flash memory |
| 01/19/1999 | US5862076 Fast EPROM array |
| 01/19/1999 | US5862072 Memory array architecture and method for dynamic cell plate sensing |
| 01/19/1999 | US5861767 For generating a signal for controlling current |
| 01/19/1999 | US5861662 Anti-tamper bond wire shield for an integrated circuit |
| 01/19/1999 | US5861652 Features a molding compound having an associated capacitanceencapsulates the substrate, the first and second circuits |
| 01/19/1999 | CA2119200C Burst srams for use with a high speed clock |
| 01/14/1999 | WO1998036587A3 Queuing structure and method for prioritization of frames in a network switch |
| 01/14/1999 | DE19729277A1 Transferable polarisation trap arrangement for opto-electronic signal processing |
| 01/13/1999 | EP0890953A2 Memory device providing burst read access and write access from a single address input |
| 01/13/1999 | EP0890173A1 Circuit arrangement with a plurality of electronic circuit components |
| 01/13/1999 | EP0890172A1 Solid-state memory device |
| 01/13/1999 | CN1204859A Current detection type sense amplifier |
| 01/12/1999 | US5860135 File managing device of a non-volatile memory, a memory card and method for controlling a file system |
| 01/12/1999 | US5860128 Method for accessing a memory |
| 01/12/1999 | US5860084 Method for reading data in a memory cell |
| 01/12/1999 | US5860076 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses |
| 01/12/1999 | US5859810 Pulse generation circuit and method for synchronized data loading in an output pre-buffer |
| 01/12/1999 | US5859807 Semiconductor integrated circuit device having a controlled overdriving circuit |
| 01/12/1999 | US5859806 Semiconductor memory device and computer |
| 01/12/1999 | US5859805 Dynamic semiconductor memory device having an improved sense amplifier layout arrangement |
| 01/12/1999 | US5859800 Data holding circuit and buffer circuit |
| 01/12/1999 | US5859793 Synchronous semiconductor memory device |
| 01/12/1999 | US5859544 Dynamic configurable elements for programmable logic devices |
| 01/12/1999 | CA2080252C Information processing apparatus |
| 01/07/1999 | WO1999000797A2 Node-precise voltage regulation for a mos memory system |
| 01/07/1999 | WO1999000734A1 Memory module and data processing system |
| 01/07/1999 | EP0889480A2 Improved dynamic access memory equalizer circuits and methods therefor |
| 01/07/1999 | EP0889477A1 Data processor with built-in dram |
| 01/07/1999 | DE19807298A1 Synchronous semiconductor memory arrangement |
| 01/06/1999 | CN1204126A Synchronous semiconductor memory device capable of reducing electricity consumption on standby |
| 01/06/1999 | CN1041581C Semiconductor memory and method of setting type |
| 01/05/1999 | USRE36027 Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages |
| 01/05/1999 | US5857095 Method for aligning a control signal and a clock signal |
| 01/05/1999 | US5856950 Cancellation of redundant elements with a cancel bank |
| 01/05/1999 | US5856949 Current sense amplifier for RAMs |
| 01/05/1999 | US5856947 Integrated DRAM with high speed interleaving |
| 01/05/1999 | US5856939 Low voltage dynamic memory |
| 01/05/1999 | US5856748 Sensing amplifier with current mirror |
| 01/05/1999 | CA2163580C Synchronous memory device |
| 12/30/1998 | WO1998059343A1 Synchronous page-mode non-volatile memory |
| 12/30/1998 | EP0887804A1 Read method and circuit for dynamic memory |
| 12/30/1998 | EP0887802A2 Method for operating a memory |
| 12/30/1998 | EP0887801A2 Apparatus for controlling circuit response during power-up |
| 12/30/1998 | EP0887734A2 High speed electrical signal interconnect structure |
| 12/29/1998 | US5854771 Semiconductor memory device including copy circuit |
| 12/29/1998 | US5854767 Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit |
| 12/29/1998 | US5854765 Semiconductor memory device |
| 12/29/1998 | US5854761 Cache memory array which stores two-way set associative data |
| 12/29/1998 | US5854636 Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit |
| 12/29/1998 | US5854635 Video storage device |
| 12/29/1998 | US5854562 Sense amplifier circuit |
| 12/23/1998 | WO1998058381A1 Method and apparatus for local control signal generation in a memory device |
| 12/23/1998 | WO1998058380A1 Variable voltage isolation gate |
| 12/23/1998 | CN1202763A Delay circuit device |
| 12/22/1998 | US5852586 Single-chip synchronous dynamic random access memory (DRAM) system including first address generator operable in first and second modes |
| 12/22/1998 | US5852584 Dynamic random access memory of a plurality of banks exhibiting high speed activation operation of sense amplifier |
| 12/22/1998 | US5852580 Repair fuse circuit in a flash memory device |
| 12/22/1998 | US5852579 Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory |
| 12/22/1998 | CA2109835C Differential latching inverter and random access memory using same |
| 12/17/1998 | WO1998057332A1 Semiconductor circuit and method of controlling the same |
| 12/17/1998 | WO1998057331A1 Two step memory device command buffer apparatus and method and memory devices and computer systems using same |
| 12/17/1998 | WO1998057330A1 Method and system for storing and processing multiple memory addresses |
| 12/17/1998 | WO1998057241A1 Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data |
| 12/16/1998 | EP0884846A1 Delay circuit with calibration method |
| 12/16/1998 | EP0884733A2 Self timed precharge sense amplifier for a memory array |
| 12/16/1998 | EP0884732A2 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |