| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/28/1999 | CN1215250A Secondary read out amplifier with window discriminator for self-timing operation |
| 04/28/1999 | CN1215211A Dynamic type semiconductor memory device with valve value compensation function |
| 04/27/1999 | USRE36203 Semiconductor memory circuit |
| 04/27/1999 | US5898895 System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing |
| 04/27/1999 | US5898640 Even bus clock circuit |
| 04/27/1999 | US5898639 Memory with variable write driver operation |
| 04/27/1999 | US5898632 Sense amplifier of virtual ground flat-cell |
| 04/27/1999 | US5898631 Semiconductor storage |
| 04/27/1999 | US5898628 Data transfer circuit |
| 04/27/1999 | US5898625 Fast power up reference voltage circuit and method |
| 04/27/1999 | US5898624 Noise restraining semiconductor memory device |
| 04/27/1999 | US5898623 Input port switching protocol for a random access memory |
| 04/27/1999 | US5898622 Read circuit for memory |
| 04/27/1999 | US5898619 Memory cell having a plural transistor transmission gate and method of formation |
| 04/27/1999 | US5898605 Apparatus and method for simplified analog signal record and playback |
| 04/27/1999 | US5898343 Voltage and temperature compensated ring oscillator for a memory device |
| 04/27/1999 | US5898331 Semiconductor memory having signal input circuit of synchronous type |
| 04/27/1999 | US5897668 Memory system for storing information data and state-of-radio-transmission data |
| 04/27/1999 | US5897659 Modifying RAS timing based on wait states to accommodate different speed grade DRAMs |
| 04/27/1999 | CA2145365C Method for accessing banks of dram |
| 04/22/1999 | WO1999019877A1 Programmable logic device memory cell circuit |
| 04/22/1999 | WO1999019876A1 Apparatus and method for device timing compensation |
| 04/22/1999 | WO1999019875A2 Apparatus and method for pipelined memory operations |
| 04/22/1999 | WO1999019874A1 Power control system for synchronous memory device |
| 04/22/1999 | WO1999019805A1 Method and apparatus for two step memory write operations |
| 04/21/1999 | EP0910091A2 Dual-port programmable logic device variable depth and width memory array |
| 04/21/1999 | CN1214793A Semiconductor memory device |
| 04/21/1999 | CN1214792A Circuit arrangement with plurality of electronic circuit components |
| 04/21/1999 | CN1214518A Burst mode type semiconductor memory device |
| 04/21/1999 | CN1214515A Semiconductor memory |
| 04/21/1999 | CN1214514A Write control driver circuit |
| 04/20/1999 | US5896551 Initializing and reprogramming circuitry for state independent memory array burst operations control |
| 04/20/1999 | US5896404 Programmable burst length DRAM |
| 04/20/1999 | US5896395 Integrated circuit memory devices and operating methods including temporary data path width override |
| 04/20/1999 | US5896347 Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same |
| 04/20/1999 | US5896346 High speed and low cost SDRAM memory subsystem |
| 04/20/1999 | US5896343 Semiconductor memory device having additional driver circuit for reducing signal propagation delay |
| 04/20/1999 | US5896342 Semiconductor memory device having collective writing mode for writing data on row basis |
| 04/20/1999 | US5896339 Multi-bit block write in a random access memory |
| 04/20/1999 | US5896337 Circuits and methods for multi-level data through a single input/ouput pin |
| 04/20/1999 | US5896336 Device and method for driving a conductive path with a signal |
| 04/20/1999 | US5896335 Method and apparatus for reducing power dissipation in a precharge/discharge memory system |
| 04/20/1999 | US5896332 Method and apparatus for measuring the offset voltages of SRAM sense amplifiers |
| 04/20/1999 | US5896329 Repairable memory cell for a memory cell array |
| 04/20/1999 | US5896323 Data output control circuit for semiconductor memory device |
| 04/20/1999 | US5896310 Multiple bank memory with over-the-array conductors programmable for providing either column factor or y-decoder power connectivity |
| 04/20/1999 | US5896052 Methods to avoid instability |
| 04/20/1999 | US5895482 Data transfer system for transferring data in synchronization with system clock and synchronous semiconductor memory |
| 04/15/1999 | WO1999005782A3 Sense amplifier for complementary or non-complementary data signals |
| 04/15/1999 | WO1998055897B1 Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device |
| 04/15/1999 | DE19825034A1 Level shifting circuit for memory circuit e.g. DRAM |
| 04/14/1999 | EP0908892A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0908890A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0908889A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0908888A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0908887A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0908886A2 Semiconductor integrated circuit device |
| 04/14/1999 | EP0803124B1 A dual bank memory and systems using the same |
| 04/14/1999 | EP0765498A4 Flash memory based main memory |
| 04/14/1999 | EP0677849B1 Multiple I/O select memory |
| 04/14/1999 | CN1213834A High density semiconductor memory having diagonal bit lines and dual word lines |
| 04/14/1999 | CN1213833A Semiconductor memory device |
| 04/13/1999 | US5894442 Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal |
| 04/13/1999 | US5894440 Semiconductor memory device and data transferring structure and method therein |
| 04/13/1999 | US5894439 Memory device |
| 04/13/1999 | US5894437 Concurrent read/write architecture for a flash memory |
| 04/13/1999 | US5894433 Static memory cell having independent data holding voltage |
| 04/13/1999 | US5894431 Low power output block for large ROM |
| 04/13/1999 | US5894233 Sense amplifiers including bipolar transistor input buffers and field effect transistor latch circuits |
| 04/13/1999 | US5894229 Input circuit of semiconductor memory device for generating an internal signal in accordance with an external signal and for applying it to an internal circuitry |
| 04/13/1999 | US5893927 Memory device having programmable device width, method of programming, and method of setting device width for memory device |
| 04/13/1999 | US5893925 Synchronous semiconductor memory device in which burst counter is commonly employed for data writing and for data reading |
| 04/08/1999 | DE19820040A1 Semiconductor memory |
| 04/08/1999 | DE19758514A1 Circuit for erasing a CMOS RAM memory |
| 04/08/1999 | DE19743666A1 Subdivision of memory capacity in car radio system |
| 04/07/1999 | EP0906620A1 Device and method for recording an information signal in a recording carrier |
| 04/07/1999 | CN1213142A Semiconductor memory with built-in row buffer and method of driving the same |
| 04/07/1999 | CN1213141A Semiconductor memory with high space-efficient MDQ switch placement |
| 04/07/1999 | CN1213140A Indicator circuit with small placeholder, high speed and low power dissipation |
| 04/06/1999 | US5893168 Structure and method for memory initialization and power on |
| 04/06/1999 | US5893167 Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access |
| 04/06/1999 | US5893135 Flash memory array with two interfaces for responding to RAS and CAS signals |
| 04/06/1999 | US5892979 Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold |
| 04/06/1999 | US5892777 Apparatus and method for observing the mode of a memory device |
| 04/06/1999 | US5892730 Synchronous semiconductor memory device operable in a plurality of data write operation modes |
| 04/06/1999 | US5892728 Column decoder configuration for a 1T/1C ferroelectric memory |
| 04/06/1999 | US5892725 Memory in a data processing system having uneven cell grouping on bitlines and method therefor |
| 04/06/1999 | US5892724 NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines |
| 04/06/1999 | US5892723 Potential difference transmission device and semiconductor memory device using the same |
| 04/06/1999 | US5892722 Column selection circuit |
| 04/06/1999 | US5892713 Nonvolatile semiconductor memory device |
| 04/06/1999 | US5892384 Timing signal generation circuit |
| 04/01/1999 | WO1999016078A1 Synchronous integrated circuit device |
| 04/01/1999 | DE19742369A1 Digital audio signal recording and reproduction device |
| 03/31/1999 | EP0905785A2 High density semiconductor memory |
| 03/31/1999 | EP0905709A2 Single ended match sense amplifier |
| 03/31/1999 | EP0905706A2 Pointer circuit with reduced surface, high speed and low power dissipation |
| 03/31/1999 | EP0905703A2 Semiconductor memory having space-efficient layout |
| 03/31/1999 | EP0905702A2 Secondery sense amplifier with window discriminator for self-timed operation |
| 03/31/1999 | EP0905701A2 Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines |