Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
06/2003
06/12/2003US20030107911 Semiconductor memory device
06/12/2003US20030107910 Integrated memory, and a method of operating an integrated memory
06/12/2003US20030107849 Magnetic device using ferromagnetic film, magnetic recording medium using ferromagnetic film, and device using ferroelectric film
06/12/2003US20030107414 Data output buffer
06/12/2003US20030107362 Voltage generator circuit for use in a semiconductor device
06/12/2003US20030107105 Programmable chip-to-substrate interconnect structure and device and method of forming same
06/12/2003US20030107057 Tunneling magnetoresistive storage unit
06/11/2003EP1318591A2 A semiconductor booster circuit requiring no transistor elements having a breakdown voltage of substantially twice the power supply voltage
06/11/2003EP1318523A1 Method of controlling magnetization easy axis in ferromagnetic films using voltage, ultrahigh-density, low power, nonvolatile magnetic memory using the control method and method of writing information on the magnetic memory
06/11/2003EP1318522A2 Memory devices
06/11/2003EP1072040B1 Non-volatile storage latch
06/11/2003EP0888618B1 Second-layer phase change memory array on top of a logic device
06/11/2003CN1423420A Multi-threshold MIS integrated circuit device and circuit designing method
06/11/2003CN1423337A SNNNS non-volatile memory unit data writing-in and deleting method
06/11/2003CN1423335A Semiconductor memory device
06/11/2003CN1423334A Storage device with storage unit with four states
06/11/2003CN1423332A Electric-level moving device
06/11/2003CN1423284A Semiconductor integrated circuit comprising storage macro
06/11/2003CN1423283A Semiconductor storage circuit not easy to make soft mistakes
06/11/2003CN1423282A Storage device
06/11/2003CN1423281A Magnetic random-access storage device and reading method thereof
06/11/2003CN1423280A Write current compensation for storing temp. change in array
06/11/2003CN1423279A Semiconductor storage device reading data according to current passing through storage anit while accessing
06/10/2003US6577553 Semiconductor memory device
06/10/2003US6577550 Control circuit and semiconductor memory device
06/10/2003US6577549 Write current compensation for temperature variations in memory arrays
06/10/2003US6577548 Self timing interlock circuit for embedded DRAM
06/10/2003US6577545 Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same
06/10/2003US6577543 Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other
06/10/2003US6577541 Semiconductor integrated circuit device and control method therefor
06/10/2003US6577532 Method for performing analog over-program and under-program detection for a multistate memory cell
06/10/2003US6577530 Semiconductor memory device having memory cells each capable of storing three or more values
06/10/2003US6577529 Multi-bit magnetic memory device
06/10/2003US6577528 Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration
06/10/2003US6577527 Method for preventing unwanted programming in an MRAM configuration
06/10/2003US6577526 Magnetoresistive element and the use thereof as storage element in a storage cell array
06/10/2003US6577525 Sensing method and apparatus for resistance memory device
06/10/2003US6577523 Reduced area sense amplifier isolation layout in a dynamic RAM architecture
06/10/2003US6577522 Semiconductor memory device including an SOI substrate
06/10/2003US6577175 Method for generating internal clock of semiconductor memory device and circuit thereof
06/10/2003US6577124 Magnetic field sensor with perpendicular axis sensitivity, comprising a giant magnetoresistance material or a spin tunnel junction
06/10/2003US6576969 Magneto-resistive device having soft reference layer
06/10/2003US6576962 CMOS SRAM cell with prescribed power-on data state
06/10/2003US6576921 By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced
06/10/2003US6576517 Method for obtaining a multi-level ROM in an EEPROM process flow
06/10/2003US6576480 Structure and method for transverse field enhancement
06/05/2003WO2003047104A1 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
06/05/2003WO2003046995A1 Matrix-addressable apparatus with one or more memory devices
06/05/2003WO2003046990A2 Method and apparatus for standby power reduction in semiconductor devices
06/05/2003WO2003046924A1 Folded memory layers
06/05/2003WO2003046923A1 A method for reading a passive matrix-addressable device and a device for performing the method
06/05/2003WO2003046922A2 Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-write memory cells
06/05/2003WO2003046918A2 High performance semiconductor memory devices
06/05/2003US20030106010 Memory circuit having parity cell array
06/05/2003US20030106001 Semiconductor integrated circuit including memory macro
06/05/2003US20030105916 Semiconductor memory device
06/05/2003US20030105907 System and method for caching DRAM using an egress buffer
06/05/2003US20030104674 Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same
06/05/2003US20030104637 Method for manufacturing quantum dotbased manetic random access memory ( mram)
06/05/2003US20030104636 Method and article for concentrating fields at sense layers
06/05/2003US20030104229 Polymers comprised of sandwich coordination compounds, such as Eu or Ce coordinated porphyrins and phthalocyanines; electrochromic displays, molecular capacitors, and batteries.
06/05/2003US20030103407 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
06/05/2003US20030103406 Digital multilevel memory system having multistage autozero sensing
06/05/2003US20030103405 Voltage detection level correction circuit and semiconductor device
06/05/2003US20030103404 Magnetic tunnel junction magnetic random access memory
06/05/2003US20030103403 Semiconductor integrated circuit with reduction of self refresh current
06/05/2003US20030103402 Write current compensation for temperature variations in memory arrays
06/05/2003US20030103401 Write current compensation for temperature variations in memory arrays
06/05/2003US20030103400 Multistage autozero sensing for a multilevel non-volatile memory integrated circuit system
06/05/2003US20030103399 Semiconductor memory device
06/05/2003US20030103398 Sub-volt sensing for digital multilevel flash memory
06/05/2003US20030103397 Semiconductor memory device and sensing control method having more stable input/output line sensing control
06/05/2003US20030103396 Semiconductor memory device capable of switching output data width
06/05/2003US20030103395 Semiconductor memory device reading data based on memory cell passing current during access
06/05/2003US20030103394 Semiconductor storage device and method for remedying defects of memory cells
06/05/2003US20030103393 Magnetic memory device and method for manufacturing the same
06/05/2003US20030103391 Ferroelectric memory cell array and device for operating the same
06/05/2003US20030103389 Serial access memory
06/05/2003US20030103386 Method for reading a passive matrix-addressable device and a device for performing the method
06/05/2003US20030103380 Programming methods for multi-level flash EEPROMs
06/05/2003US20030103378 Magnetic random access memory
06/05/2003US20030103377 Magnetic random access memory
06/05/2003US20030103376 Method for driving memory cells of a dynamic semiconductor memory and circuit configuration
06/05/2003US20030103375 Junction-isolated depletion mode ferroelectric memory devices
06/05/2003US20030103374 Memory device
06/05/2003US20030103373 Nonvolatile ferroelectric memory device and method for operating main bitline load controller thereof
06/05/2003US20030103372 Ferroelectric memory and operating method therefor
06/05/2003US20030103371 Method of controlling magnetization easy axis in ferromagnetic films using voltage, ultrahigh-density, low power, nonvolatile magnetic memory using the control method, and method of writing information on the magnetic memory
06/05/2003US20030103370 Ferroelectric memory device and method to sequentially link same
06/05/2003US20030103369 Extensible/retractable and storable portable memory device
06/05/2003US20030103368 Refresh-free dynamic semiconductor memory device
06/05/2003US20030103367 Quantum dot-based magnetic random access memory (mram) and method for manufacturing same
06/05/2003US20030103109 Ink ejection mechanism having a thermal actuator that undergoes rectilinear motion
06/05/2003US20030103097 Ejection of ink using pulsating pressure and a movable shutter
06/05/2003US20030103025 Display device and display system using the same
06/05/2003US20030102904 Semiconductor integrated circuit device
06/05/2003US20030102902 Semiconductor integrated circuit
06/05/2003US20030102901 Temperature dependent circuit, and current generating circuit, inverter and oscillation circuit using the same
06/05/2003US20030102881 Method and apparatus for reducing the current consumption of an electronic circuit
06/05/2003US20030102514 Static random access memory and semiconductor device using mos transistors having channel region electrically connected with gate