Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2003
11/19/2003CN1457100A Semiconductor memory
11/19/2003CN1456959A Semiconductor memory compoent face down chip interface circuit and face down chip interface method
11/19/2003CN1128450C Nonvolatile memory cell and method for programming method
11/19/2003CN1128449C Semiconductor storage device
11/19/2003CN1128437C Quick magnetization coversion method, apparatus and magnetizing media
11/18/2003US6651204 Modular architecture for memory testing on event based test system
11/18/2003US6651203 On chip programmable data pattern generator for semiconductor memories
11/18/2003US6651134 Memory device with fixed length non interruptible burst
11/18/2003US6651032 Setting data retention thresholds in charge-based memory
11/18/2003US6651022 Semiconductor device capable of test mode operation
11/18/2003US6650594 Device and method for selecting power down exit
11/18/2003US6650593 Memory system having memory controller for controlling different types of memory chips
11/18/2003US6650590 Semiconductor memory device with reduced its chip area and power consumption
11/18/2003US6650589 Low voltage operation of static random access memory
11/18/2003US6650588 Semiconductor memory module and register buffer device for use in the same
11/18/2003US6650587 Partial array self-refresh
11/18/2003US6650586 Circuit and system for DRAM refresh with scoreboard methodology
11/18/2003US6650584 Full stress open digit line memory device
11/18/2003US6650583 Test circuit device capable of identifying error in stored data at memory cell level and semiconductor integrated circuit device including the same
11/18/2003US6650582 Semiconductor memory device
11/18/2003US6650581 Semiconductor memory device, and method for testing the same
11/18/2003US6650574 Semiconductor device preventing signal delay among wirings
11/18/2003US6650573 Data input/output method
11/18/2003US6650572 Compact analog-multiplexed global sense amplifier for rams
11/18/2003US6650570 Non-volatile semiconductor memory
11/18/2003US6650568 Method of read operation of nonvolatile semiconductor memory and nonvolatile semiconductor memory
11/18/2003US6650565 Semiconductor memory device
11/18/2003US6650564 System and method for enabling chip level erasing and writing for magnetic random access memory devices
11/18/2003US6650563 Compact and highly efficient DRAM cell
11/18/2003US6650562 System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
11/18/2003US6650173 Programmable voltage generator
11/18/2003US6650158 Ferroelectric non-volatile logic elements
11/18/2003US6650152 Intermediate voltage control circuit having reduced power consumption
11/18/2003US6649984 Logic-merged memory
11/18/2003US6649972 Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
11/18/2003US6649963 Ferroelectric memory cell for VLSI RAM
11/18/2003US6649960 Synthetic free layer structure for MRAM devices
11/18/2003US6649953 Magnetic random access memory having a transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell
11/18/2003US6649931 Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device
11/18/2003US6649542 Multi-level type nonvolatile semiconductor memory device
11/18/2003US6649470 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
11/18/2003US6649467 Method of making high density semiconductor memory
11/18/2003US6649423 Method for modifying switching field characteristics of magnetic tunnel junctions
11/18/2003US6648453 Ink jet printhead chip with predetermined micro-electromechanical systems height
11/13/2003WO2003094201A2 High voltage row and column driver for programmable resistance memory
11/13/2003WO2003094182A1 Method of forming mram devices
11/13/2003WO2003094171A1 Molecular wire crossbar flash memory
11/13/2003WO2003094170A2 Layout for thermally selected cross-point mram cell
11/13/2003WO2003083429A8 A novel highly-integrated flash memory and mask rom array architecture
11/13/2003WO2003081598A3 Method and system for maximizing dram memory bandwidth
11/13/2003WO2003079362A3 Circuit arrangement for sensing and evaluating a charge state and rewriting the latter to a memory cell
11/13/2003WO2003067600A3 Antiferromagnetically stabilized pseudo spin valve for memory applications
11/13/2003WO2003067598A3 Reading circuit for reading a memory cell
11/13/2003WO2003025947A3 Edram based architecture
11/13/2003WO2002099661A3 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
11/13/2003US20030212925 Memory circuit testing system, semiconductor device, and memory testing method
11/13/2003US20030212725 Methods of factoring and modular arithmetic
11/13/2003US20030212724 Methods of computing with digital multistate phase change materials
11/13/2003US20030211726 Surface-smoothing conductive layer for semiconductor devices with magnetic material layers
11/13/2003US20030211722 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line
11/13/2003US20030211679 Flip chip interface circuit of a semiconductor memory device and method for interfacing a flip chip
11/13/2003US20030210604 Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time
11/13/2003US20030210600 Semiconductor memory device with mode register and method for controlling deep power down mode therein
11/13/2003US20030210598 Implementation of a temperature sensor to control internal chip voltages
11/13/2003US20030210597 Information storage apparatus, information storage method, recording medium and program
11/13/2003US20030210596 Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus
11/13/2003US20030210595 Semiconductor device with self refresh test mode
11/13/2003US20030210594 Semiconductor memory device having multi-bit testing function
11/13/2003US20030210591 Magnetic memory device and magnetic substrate
11/13/2003US20030210586 Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
11/13/2003US20030210584 Column decoder configuration for a 1T/1C memory
11/13/2003US20030210578 DLL driving circuit for use in semiconductor memory device
11/13/2003US20030210577 Semiconductor memory device
11/13/2003US20030210575 Multimode data buffer and method for controlling propagation delay time
11/13/2003US20030210569 Semiconductor memory device and memory system
11/13/2003US20030210566 Semiconductor memory device
11/13/2003US20030210565 Split local and continuous bitline for fast domino read sram
11/13/2003US20030210506 Use of DQ pins on a ram memory chip for a temperature sensing protocol
11/13/2003US20030210505 Use of an on-die temperature sensing scheme for thermal protection of DRAMS
11/13/2003US20030210300 Inkjet printhead with hollow drop ejection chamber formed partly of actuator material
11/13/2003US20030210090 Internal power voltage generating circuit of semiconductor memory device and internal power voltage controlling method thereof
11/13/2003US20030209971 Programmable structure, an array including the structure, and methods of forming the same
11/13/2003US20030209770 Unipolar spin transistor and the applications of the same
11/13/2003US20030209769 Multi-bit MRAM device with switching nucleation sites
11/13/2003US20030209754 Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
11/13/2003US20030209739 Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode
11/13/2003US20030209728 Microelectronic programmable device and methods of forming and programming the same
11/12/2003EP1361580A2 Semiconductor memory device, and method of controlling the same
11/12/2003EP1360694A1 Volumetric electro optical recording
11/12/2003EP1360692A2 Method for writing into magnetoresistive memory cells and magnetoresistive memory which can be written into according to said method
11/12/2003CN1455545A Double-processor apparatus capable of pulsing and writing data at same time
11/12/2003CN1455463A Magnetic controlled resistance storage device with magnetic field attenuation layer
11/12/2003CN1455415A Semiconductor storage apparatus
11/12/2003CN1455414A Resistance crosspoint storage unit array having cross-coupling latch reading amplifier
11/12/2003CN1455413A Differencial current estimation circuit of estimating memory state of static random memory semiconductor memory cell unit and reading amplifying circuit
11/12/2003CN1455412A Resistance crosspoint storage array with charge injection differential read-out amplifier
11/12/2003CN1127800C Secondary read out amplifier with window discriminator for self-timing operation
11/12/2003CN1127766C Semiconductor storage apparatus
11/11/2003US6647478 Semiconductor memory device
11/11/2003US6647470 Memory device having posted write per command
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