| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 07/13/2004 | US6762952 Minimizing errors in a magnetoresistive solid-state storage device |
| 07/13/2004 | US6762951 Semiconductor integrated circuit device |
| 07/13/2004 | US6762950 Folded memory layers |
| 07/13/2004 | US6762949 Dynamic RAM-and semiconductor device |
| 07/13/2004 | US6762948 Semiconductor memory device having first and second memory architecture and memory system using the same |
| 07/13/2004 | US6762639 Booster circuit capable of switching between a conventional mode and a low consumption current mode |
| 07/13/2004 | US6762620 Circuit and method for controlling on-die signal termination |
| 07/13/2004 | US6762481 Electrically programmable nonvolatile variable capacitor |
| 07/08/2004 | WO2004057623A1 Non-volatile memory and write method thereof |
| 07/08/2004 | WO2004057621A1 Cmis semiconductor nonvolatile storage circuit |
| 07/08/2004 | WO2004057620A2 Method and system for performing memory operations of a memory device |
| 07/08/2004 | WO2004034400A3 Sense amplifier with configurable voltage swing control |
| 07/08/2004 | WO2004029980A3 Refresh control circuit for ics with a memory array |
| 07/08/2004 | WO2004012197A3 Magnetoresistive random access memory with soft magnetic reference layer |
| 07/08/2004 | WO2003098632A3 Methods of fabricating magnetoresistive memory devices |
| 07/08/2004 | WO2003058652A3 Electromechanical three-trace junction devices |
| 07/08/2004 | US20040133763 Computing architecture and related system and method |
| 07/08/2004 | US20040133758 Memory controller, interface device and method using a mode selection signal to support different types of memories |
| 07/08/2004 | US20040133736 Memory module device for use in high-frequency operation |
| 07/08/2004 | US20040133735 Dram and dram refresh method |
| 07/08/2004 | US20040133730 Fast random access DRAM management method |
| 07/08/2004 | US20040132250 Preventing dielectric thickening over a gate area of a transistor |
| 07/08/2004 | US20040130960 Bit line control for low power in standby |
| 07/08/2004 | US20040130959 Semiconductor memory device having a DRAM cell structure and handled as a SRAM |
| 07/08/2004 | US20040130958 Semiconductor memory device |
| 07/08/2004 | US20040130957 Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor |
| 07/08/2004 | US20040130955 Magnetic memory, magnetic memory array, method for fabricating a magnetic memory, method for recording in a magnetic memory and method for reading out from a magnetic memory |
| 07/08/2004 | US20040130947 Flash memory with trench select gate and fabrication process |
| 07/08/2004 | US20040130946 Storing data in-non-volatile memory devices |
| 07/08/2004 | US20040130945 Integrated circuit memory devices and methods of programming the same in which the current drawn during a programming operation is independent of the data to be programmed |
| 07/08/2004 | US20040130943 Nonvolatile semiconductor memory device |
| 07/08/2004 | US20040130941 Multibit metal nanocrystal memories and fabrication |
| 07/08/2004 | US20040130940 Magnetic element utilizing spin transfer and an MRAM device using the magnetic element |
| 07/08/2004 | US20040130939 Nonvolatile semiconductor memory device |
| 07/08/2004 | US20040130938 Semiconductor memory device and control method thereof |
| 07/08/2004 | US20040130937 High reliable reference current generator for MRAM |
| 07/08/2004 | US20040130936 Spin-transfer multilayer stack containing magnetic layers with resettable magnetization |
| 07/08/2004 | US20040130935 Ferromagnetic resonance switching for magnetic random access memory |
| 07/08/2004 | US20040130934 NROM memory cell, memory array, related devices and methods |
| 07/08/2004 | US20040130933 Semiconductor memory device |
| 07/08/2004 | US20040130931 Semiconductor memory device with memory cell having low cell ratio |
| 07/08/2004 | US20040130930 Column voltage control for write |
| 07/08/2004 | US20040130929 MRAM architecture with a flux closed data storage layere |
| 07/08/2004 | US20040130928 Ferro-electric random access memory |
| 07/08/2004 | US20040130927 Pipeline accelerator having multiple pipeline units and related computing machine and method |
| 07/08/2004 | US20040130926 Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing |
| 07/08/2004 | US20040130924 Multiple match detection circuit and method |
| 07/08/2004 | US20040130599 Ink jet printhead with amorphous ceramic chamber |
| 07/08/2004 | US20040130473 Current folding cell and circuit comprising at least one folding cell |
| 07/08/2004 | US20040130251 Emitter and method of making |
| 07/08/2004 | US20040129987 Ferroelectric composite material, method of making same and memory utilizing same |
| 07/08/2004 | US20040129963 Semiconductor device and manufacturing method thereof |
| 07/08/2004 | US20040129961 ferroelectric film comprises ferroelectric layered superlattice comprising strontium bismuth tantalate or strontium bismuth tantalum niobate; large surface area; vapor depositing conformal top electrode layer |
| 07/08/2004 | US20040129952 Integrated circuit with programmable fuse array |
| 07/08/2004 | US20040129928 Method for modifying switching field characteristics of magnetic tunnel junctions |
| 07/08/2004 | US20040129789 Data distribution mechanism in the form of ink dots on cards |
| 07/08/2004 | US20040129670 Method for fabricating ferroelectric random access memory device |
| 07/08/2004 | DE19649704B4 Synchrone Halbleiterspeichereinrichtung mit einer Ausgabesteuerschaltung mit reduzierter belegter Fläche The synchronous semiconductor memory device having an output control circuit having a reduced occupied area |
| 07/08/2004 | DE19618781B4 Halbleiterspeichervorrichtung mit hierarchischer Spaltenauswahlleitungsstruktur A semiconductor memory device having a hierarchical column select line structure |
| 07/08/2004 | DE19604764B4 Halbleiterspeichereinrichtung und Verfahren zum Auswählen einer Wortleitung in einer Halbleiterspeichereinrichtung A semiconductor memory device and method for selecting a word line in a semiconductor memory device |
| 07/08/2004 | DE10355273A1 Magnetic random access memory device for storing data, has elongated reference magnetic resistors extending along face nonparallel to main magnetic resistors and including resistance between maximum and minimum resistance |
| 07/08/2004 | DE10342359A1 MRAM mit zwei Schreibleitern MRAM with two write heads |
| 07/08/2004 | DE10338047A1 Semiconducting memory device has memory cells in rows/columns, two word lines between adjacent bit line contacts in column direction; each bit line contact separates two adjacent cells in column direction |
| 07/08/2004 | DE10258168A1 Integrated semiconductor memory to act as dynamic random access memory (DRAM) has local data lines segmented as a column each being linked to sense amplifiers in read/write cycles |
| 07/08/2004 | DE10239322B4 Integrierter Speicher und Verfahren zur Einstellung der Latenzzeit im integrierten Speicher Integrated memory and method for adjusting the latency integrated memory |
| 07/08/2004 | DE10232962B4 Schaltung und Verfahren zum Schreiben und Auslesen von Daten aus einer dynamischen Speicherschaltung Circuit and method for writing and reading out data from a dynamic memory circuit |
| 07/08/2004 | DE10147137B4 DRAM-Anordnung mit Speicherzellen mit bipolarem Trenntransistor, dessen Emitter auf konstantem Plattenpotential liegt DRAM device having memory cells with bipolar isolation transistor whose emitter is at a constant potential plate |
| 07/07/2004 | EP1435623A1 Stabilisation method of the drain voltage in non-volatile multilevel memory cells and relating memory device |
| 07/07/2004 | EP1435622A2 Magnetic random access memory for storing information utilizing magneto-resistive effects |
| 07/07/2004 | EP1435574A2 A structure and method for detecting errors in a multilevel memory device with improved programming granularity |
| 07/07/2004 | EP1435101A1 Spin-valve magnetoresistive device with enhanced performance |
| 07/07/2004 | EP1435098A2 Mram bit line word line architecture |
| 07/07/2004 | EP1435097A2 Adjustable memory self-timing circuit |
| 07/07/2004 | EP1043774B1 Semiconductor integrated circuit |
| 07/07/2004 | CN1511323A Dynamic memory and method for testing dynamic memory |
| 07/07/2004 | CN1511322A 半导体存储器 Semiconductor memory |
| 07/07/2004 | CN1510752A Semiconductor device with redundant function |
| 07/07/2004 | CN1510751A Semiconductor devices |
| 07/07/2004 | CN1510692A Nonvolatile memory with write protection zone |
| 07/07/2004 | CN1510690A Semiconductor memory apparatus and data write method |
| 07/07/2004 | CN1510689A Flash memory data recording/reading method and circuit |
| 07/07/2004 | CN1510688A Semiconductor memory and controlling method thereof |
| 07/07/2004 | CN1510687A Semiconductor memory and semiconductor device |
| 07/07/2004 | CN1510686A Magnetic random access memory element with unparalleled main magnetic resistance and reference resistance |
| 07/07/2004 | CN1510577A Data transferring system for high speed transference |
| 07/07/2004 | CN1510417A 生物传感器及传感单元阵列 Biosensors and sensing cell array |
| 07/07/2004 | CN1156979C Input buffer for semiconductor integrated circuit |
| 07/07/2004 | CN1156853C Operation method of ferroelectric memory |
| 07/07/2004 | CN1156852C Method for reading-out and storing ferroelectric transistor state in memory cell, and storage array |
| 07/07/2004 | CN1156851C Integrated memory with bit lead reference voltage and method for generating such voltage |
| 07/07/2004 | CN1156850C Integrated ferroelectric memory whose plate lines are selected by column decoder |
| 07/07/2004 | CN1156849C Magnetic storage structure possessing improved half selection plentiful quantity |
| 07/06/2004 | USRE38545 Semiconductor memory device |
| 07/06/2004 | US6760881 Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) |
| 07/06/2004 | US6760846 System for determining and supplying stabilized voltage from a power supply to a data processor after a fluctuating period |
| 07/06/2004 | US6760806 Low power semiconductor memory device having a normal mode and a partial array self refresh mode |
| 07/06/2004 | US6760273 Buffer using two-port memory |
| 07/06/2004 | US6760269 Semiconductor memory device capable of generating internal data read timing precisely |
| 07/06/2004 | US6760268 Method and apparatus for establishing a reference voltage in a memory |
| 07/06/2004 | US6760266 Sense amplifier and method for performing a read operation in a MRAM |