Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
01/2007
01/23/2007US7167399 Flash memory device with a variable erase pulse
01/23/2007US7167398 System and method for erasing a memory cell
01/23/2007US7167395 Non-volatile semiconductor memory
01/23/2007US7167394 Sense amplifier for reading a cell of a non-volatile memory device
01/23/2007US7167392 Non-volatile memory cell with improved programming technique
01/23/2007US7167391 Multilayer pinned reference layer for a magnetic storage device
01/23/2007US7167390 Storage device with resistive memory cells enduring repetitive data writing
01/23/2007US7167389 Magnetic random access memory with a reference cell array and dummy cell arrays
01/23/2007US7167388 Integrated circuit and method for operating an integrated circuit
01/23/2007US7167387 Variable resistance element, method of manufacturing the element, memory containing the element, and method of driving the memory
01/23/2007US7167386 Ferroelectric memory and operating method therefor
01/23/2007US7167042 Semiconductor device having logic circuit and macro circuit
01/23/2007US7167033 Data retaining circuit
01/23/2007US7167024 Methods and circuitry for implementing first-in first-out structure
01/23/2007US7166886 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
01/23/2007US7166479 Methods of forming magnetic shielding for a thin-film memory element
01/18/2007WO2007008326A2 Memory architecture with enhanced over-erase tolerant control gate scheme
01/18/2007WO2007008280A2 Method of forming super-paramagnetic cladding material on conductive lines of mram devices
01/18/2007WO2007007599A1 Memory control device
01/18/2007WO2007007371A1 Circuit simulation method, circuit simulation device and circuit simulation program
01/18/2007WO2007006909A2 Resistant memory cell
01/18/2007WO2006118653A3 Triple pulse method for mram toggle bit characterization
01/18/2007WO2006089313A3 Register read for volatile memory
01/18/2007WO2005034176A3 Apparatus and method for selectively configuring a memory device using a bi-stable relay
01/18/2007WO2004051704A3 System and method for expanding a pulse width
01/18/2007US20070016741 Selectable block protection for non-volatile memory
01/18/2007US20070016738 Nonvolatile Semiconductor Memory
01/18/2007US20070016735 Flash memory device with improved management of protection information
01/18/2007US20070016723 Semiconductor Memory Device for Storing Multivalued Data
01/18/2007US20070015294 Novel structure/method to fabricate a high-performance magnetic tunneling junction MRAM
01/18/2007US20070014182 Nonvolatile semiconductor memory device which reads by decreasing effective threshold voltage of selector gate transistor
01/18/2007US20070014178 Semiconductor memory device, and method of controlling the same
01/18/2007US20070014175 DRAM and method for partially refreshing memory cell array
01/18/2007US20070014173 Energy adjusted write pulses in phase-change memories
01/18/2007US20070014172 Memory device capable of performing high speed reading while realizing redundancy replacement
01/18/2007US20070014169 Semiconductor memory device and semiconductor integrated circuit
01/18/2007US20070014162 Nonvolatile memory device including circuit formed of thin film transistors
01/18/2007US20070014161 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations
01/18/2007US20070014160 Non-volatile semiconductor memory
01/18/2007US20070014159 Under voltage protection device
01/18/2007US20070014158 Flash memory device with improved programming performance
01/18/2007US20070014157 Semiconductor device including memory cells and current limiter
01/18/2007US20070014156 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations
01/18/2007US20070014155 Method for controlling nonvolatile memory device
01/18/2007US20070014151 Nanotube-and nanocrystal-based non-volatile memory
01/18/2007US20070014150 Phase change random access memory (PRAM) device having variable drive voltages
01/18/2007US20070014149 Magnetoresistive element
01/18/2007US20070014148 Methods and systems for attaching a magnetic nanowire to an object and apparatuses formed therefrom
01/18/2007US20070014147 Power consumption minimization in magnetic random access memory by using the effect of hole-mediated ferromagnetism
01/18/2007US20070014146 Method of forming super-paramagnetic cladding material on conductive lines of MRAM devices
01/18/2007US20070014145 Nonvolatile memory circuit based on change in MIS transistor characteristics
01/18/2007US20070014144 Method of operating a programmable resistance memory array
01/18/2007US20070014143 Magnetic spin valve with a magnetoelectric element
01/18/2007US20070013742 Printhead for use with a pulsating pressure ink supply
01/18/2007US20070013016 Method and structure for generating offset fields for use in mram devices
01/18/2007US20070012978 Junction-isolated depletion mode ferroelectric memory devices and systems
01/18/2007DE102005014723B4 Verfahren zum Initialisieren von elektronischen Schaltungseinheiten und Schaltungsvorrichtung zur Durchführung des Verfahrens A method for initializing of electronic circuit units and circuit device for implementing the method
01/17/2007EP1744324A1 Read only memory
01/17/2007EP1744322A1 Devices containing multi-bit data
01/17/2007EP1744321A1 Semiconductor memory device and information processing system
01/17/2007EP1743386A2 Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization
01/17/2007EP1743383A2 Magnetoresistive memory soi cell
01/17/2007EP1743380A1 Split-channel antifuse array architecture
01/17/2007EP1743342A1 An organic electronic circuit with functional interlayer and method for making the same
01/17/2007EP1743341A1 Bimodal operation of ferrroelectric and electret memory cells and devices
01/17/2007EP1743340A1 Non-volatile programmable memory
01/17/2007EP1743339A2 Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer
01/17/2007EP1602108A4 Multi-frequency synchronizing clock signal generator
01/17/2007CN1898799A Manufacture of semiconductor device
01/17/2007CN1898751A Method circuit and system for read error detection in a non-volatile memory array
01/17/2007CN1898749A Memory device, memory circuit and semiconductor integrated circuit having variable resistance
01/17/2007CN1898748A Method and circuit configuration for multiple charge recycling during refresh operations in a dram device
01/17/2007CN1898747A Non-volatile ferroelectric thin film device using an organic ambipolar semiconductor and method for processing such a device
01/17/2007CN1898746A Memory assembly and method for operating the same
01/17/2007CN1898744A Low voltage operation dram control circuits
01/17/2007CN1898574A High sensitivity magnetic built-in current sensor
01/17/2007CN1897156A Phase change random access memory (pram) device having variable drive voltages
01/17/2007CN1897155A Current limit circuit and semiconductor memory device
01/17/2007CN1896959A Encoder for correcting static data storage fault
01/17/2007CN1295794C Nonvolatile semiconductor memory
01/17/2007CN1295792C Serial MRAM device
01/17/2007CN1295789C Memory cell and memory device
01/17/2007CN1295709C Ferro-electric memory capable of having maximum bit line capacitance
01/17/2007CN1295708C Film magnet memory with high precision data reading structure
01/17/2007CN1295707C Magnetic storage device with magnetic shielding layer and mfg. method thereof
01/16/2007US7165206 SRAM-compatible memory for correcting invalid output data using parity and method of driving the same
01/16/2007US7165197 Apparatus and method of analyzing a magnetic random access memory
01/16/2007US7165159 Memory system
01/16/2007US7165151 Semiconductor integrated circuit and data processing system
01/16/2007US7164646 Storage device having a storage cell programmable to one of more than two storage states
01/16/2007US7164617 Memory control apparatus for synchronous memory unit with switched on/off clock signal
01/16/2007US7164614 Fuse box, semiconductor memory device having the same and setting method thereof
01/16/2007US7164609 Device for controlling data output for high-speed memory device and method thereof
01/16/2007US7164603 Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
01/16/2007US7164602 Nonvolatile semiconductor memory device including high efficiency and low cost redundant structure
01/16/2007US7164601 Multi-level nonvolatile semiconductor memory device utilizing a nonvolatile semiconductor memory device for storing binary data
01/16/2007US7164600 Reducing DQ pin capacitance in a memory device
01/16/2007US7164598 Methods of operating magnetic random access memory device using spin injection and related devices
01/16/2007US7164597 Computer systems
01/16/2007US7164596 SRAM cell with column select line