Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
03/2007
03/22/2007US20070064476 Semicoductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof
03/22/2007US20070064475 Simulating circuit for magnetic tunnel junction device
03/22/2007US20070064474 Resistance variable memory element with threshold device and method of forming the same
03/22/2007US20070064473 Phase change memory device and program method thereof
03/22/2007US20070064472 Nonvolatile semiconductor memory device performing data writing in a toggle manner
03/22/2007US20070064471 Magnetostatic communication
03/22/2007US20070064470 Semiconductor device
03/22/2007US20070064469 Display device and driving method of the same
03/22/2007US20070064468 Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device
03/22/2007US20070064462 Memory system and data transmission method
03/22/2007US20070063690 High sensitivity magnetic built-in current sensor
03/22/2007DE19860799B4 Ferroelektrische Speichervorrichtung The ferroelectric memory device
03/22/2007DE10315303B4 Halbleiter-Bauelement-Spannungsversorgung für System mit mindestens zwei, insbesondere gestapelten, Halbleiter-Bauelementen The semiconductor device for power supply system having at least two, in particular stacked, semiconductor devices
03/22/2007DE102006041646A1 Schaltung und Verfahren zur Sperrvorspannungserzeugung und Pegeldetektor hierfür Circuit and method for Sperrvorspannungserzeugung and level detector therefor
03/22/2007DE102004059671B4 Verfahren zum Aktivieren von Wortleitungen bei einem Wiederauffrischungszyklus und elektronische Speichervorrichtung zur Durchführung des Verfahrens The method for activating word lines in a refresh cycle and electronic memory device for implementing the method
03/21/2007EP1683159A4 Method, system and circuit for programming a non-volatile memory array
03/21/2007EP1568041B1 Smart verify for multi-state memories
03/21/2007EP1547101B1 Amorphous alloys for magnetic devices
03/21/2007CN1934653A Self-boosting system for flash memory cells
03/21/2007CN1934652A Method and system for providing heat assisted switching of a magnetic element utilizing spin transfer
03/21/2007CN1933207A Phase transformation memory storing unit and producing method thereof
03/21/2007CN1933163A Nonvolatile semiconductor memory devices and methods of forming the same
03/21/2007CN1933028A Nand flash memory device with burst read latency function
03/21/2007CN1933023A Phase change memory device and program method thereof
03/21/2007CN1933022A Hole annealing methods of non-volatile memory cells
03/21/2007CN1933021A Sensing margin varying circuit and method thereof
03/21/2007CN1933020A Shielded bitline architecture for dynamic random access memory (dram) arrays
03/21/2007CN1933019A File flow design for low-power dynamic random access memory
03/21/2007CN1933018A Memory system and method having point-to-point link
03/21/2007CN1933014A Semiconductor storage device, electronic apparatus, and mode setting method
03/21/2007CN1306614C Semiconductor integrated circuit having connection down-lead for bit line interconnection
03/20/2007US7194617 Method and apparatus to prevent the unauthorized copying of digital information
03/20/2007US7194580 Disk array device, method of extending storage capacity and computer program
03/20/2007US7193927 Memory device and method having banks of different sizes
03/20/2007US7193925 Low power semiconductor memory device
03/20/2007US7193922 Semiconductor integrated circuit
03/20/2007US7193919 Selective bank refresh
03/20/2007US7193918 Process for refreshing a dynamic random access memory and corresponding device
03/20/2007US7193917 Semiconductor storage device, test method therefor, and test circuit therefor
03/20/2007US7193915 Semiconductor memory device
03/20/2007US7193913 Sense amplifier circuit and read/write method for semiconductor memory device
03/20/2007US7193912 Semiconductor integrated circuit device
03/20/2007US7193907 Semiconductor integrated circuit having a power-on reset circuit in a semiconductor memory device
03/20/2007US7193906 Voltage regulating circuit and method of regulating voltage
03/20/2007US7193903 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation
03/20/2007US7193901 Monitoring the threshold voltage of frequently read cells
03/20/2007US7193900 CACT-TG (CATT) low voltage NVM cells
03/20/2007US7193899 Erase block data splitting
03/20/2007US7193898 Compensation currents in non-volatile memory read operations
03/20/2007US7193897 NAND flash memory device capable of changing a block size
03/20/2007US7193895 Redundant memory content substitution apparatus and method
03/20/2007US7193894 Clock synchronized nonvolatile memory device
03/20/2007US7193892 Magnetic switching with expanded hard-axis magnetization volume at magnetoresistive bit ends
03/20/2007US7193891 Spin based sensor device
03/20/2007US7193890 Magnetoresistive effect device, magnetic random access memory, and magnetoresistive effect device manufacturing method
03/20/2007US7193889 Switching of MRAM devices having soft magnetic reference layers
03/20/2007US7193888 Nonvolatile memory circuit based on change in MIS transistor characteristics
03/20/2007US7193887 SRAM circuitry
03/20/2007US7193886 Integrated circuit with a memory of reduced consumption
03/20/2007US7193885 Radiation tolerant SRAM bit
03/20/2007US7193884 Semiconductor memory device
03/20/2007US7193883 Input return path based on Vddq/Vssq
03/20/2007US7193882 Semiconductor memory device
03/20/2007US7193881 Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts
03/20/2007US7193880 Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
03/20/2007US7193878 Semiconductor memory device layout including increased length connection lines
03/20/2007US7193823 Magnetoresistive device exhibiting small and stable bias fields independent of device size variation
03/20/2007US7193482 Integrated circuit with tamper detection circuit
03/20/2007US7193437 Architecture for a connection block in reconfigurable gate arrays
03/20/2007US7193284 Magnetoresistance effect element, method of manufacture thereof, magnetic storage and method of manufacture thereof
03/20/2007US7193278 Static random access memories (SRAMS) having vertical transistors
03/20/2007US7193267 Cross-point resistor memory array
03/20/2007US7193239 Three dimensional structure integrated circuit
03/20/2007US7192792 Method of changing an electrically programmable resistance cross point memory bit
03/20/2007US7192787 Highly nonlinear magnetic tunnel junctions for dense magnetic random access memories
03/20/2007US7192491 Adding transition metal selected from the group consisting of 4d transition metals and 5d transition metals in to alloy of nickel-iron or cobalt-iron or cobalt-nickel for increasing damping
03/20/2007US7192119 Printhead nozzle arrangement with a micro-electromechanical shape memory alloy based actuator
03/20/2007CA2468615C A method for making self-registering non-lithographic transistors with ultrashort channel lengths
03/20/2007CA2432530C Low-power organic light emitting diode pixel circuit
03/15/2007WO2007029992A1 Multiple-valued dram
03/15/2007WO2007029333A1 Semiconductor integrated circuit
03/15/2007WO2007029320A1 Ferroelectric memory
03/15/2007WO2007028888A1 Remanent volatile memory cell
03/15/2007WO2007028583A1 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
03/15/2007US20070058476 Semiconductor memory device
03/15/2007US20070058469 Memory device and method having data path with multiple prefetch I/O configurations
03/15/2007US20070058443 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
03/15/2007US20070058441 Semiconductor device
03/15/2007US20070058440 Hole annealing methods of non-volatile memory cells
03/15/2007US20070058438 Differential amplifier circuit and semiconductor device
03/15/2007US20070058437 Interface circuit
03/15/2007US20070058436 Efficient verification for coarse/fine programming of non volatile memory
03/15/2007US20070058435 Read and erase verify methods and circuits suitable for low voltage non-volatile memories
03/15/2007US20070058433 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
03/15/2007US20070058427 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
03/15/2007US20070058426 Semiconductor memory device comprising one or more injecting bilayer electrodes
03/15/2007US20070058425 Phase change random access memory device having variable drive voltage circuit
03/15/2007US20070058424 Semiconductor memory device
03/15/2007US20070058423 Upside-down magnetoresistive random access memory
03/15/2007US20070058422 Programmable magnetic memory device