Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
02/2007
02/20/2007US7180780 Multi-level-cell programming methods of non-volatile memories
02/20/2007US7180779 Memory architecture with enhanced over-erase tolerant control gate scheme
02/20/2007US7180778 Semiconductor storage device having page copying function
02/20/2007US7180777 System and method for destructive purge of memory device
02/20/2007US7180776 Systems and methods for programming a secured CPLD on-the-fly
02/20/2007US7180775 Different numbers of bits per cell in non-volatile memory devices
02/20/2007US7180774 Semiconductor integrated circuit device including first, second and third gates
02/20/2007US7180773 Magnetic memory device
02/20/2007US7180772 High-density NVRAM
02/20/2007US7180771 Device and method for pulse width control in a phase change memory device
02/20/2007US7180770 Series diode thermally assisted MRAM
02/20/2007US7180769 World line segment select transistor on word line current source side
02/20/2007US7180768 Semiconductor memory device including 4TSRAMs
02/20/2007US7180767 Multi-level memory device and methods for programming and reading the same
02/20/2007US7180766 Semiconductor memory
02/20/2007US7180765 Ferroelectric memory
02/20/2007US7180351 Hybrid latch flip-flop
02/20/2007US7180350 Hybrid latch flip-flop
02/20/2007US7180340 Frequency multiplier capable of adjusting duty cycle of a clock and method used therein
02/20/2007US7180327 Memory module system with efficient control of on-die termination
02/20/2007US7180128 Non-volatile memory, non-volatile memory array and manufacturing method thereof
02/20/2007US7180123 Method for programming programmable eraseless memory
02/20/2007US7180113 Double-decker MRAM cell with rotated reference layer magnetizations
02/20/2007US7180087 Spin filter and a memory using such a spin filter
02/20/2007US7179712 Multibit ROM cell and method therefor
02/20/2007US7179711 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
02/20/2007US7178903 Ink jet nozzle to eject ink
02/15/2007WO2007019297A1 Memory with address-differentiated refresh rate to accommodate low-retention storage rows
02/15/2007WO2007019168A2 Variable source resistor for flash memory
02/15/2007WO2007019041A1 Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals
02/15/2007WO2007019010A1 System and method for programming cells in non-volatile integrated memory devices
02/15/2007WO2007018985A2 Method of sensing an eeprom reference cell
02/15/2007WO2007006909A3 Resistant memory cell
02/15/2007WO2006033832A3 New compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device
02/15/2007US20070038852 Configuration of a multilevel flash memory device
02/15/2007US20070038803 Transparent SDRAM in an embedded environment
02/15/2007US20070036016 Nonvolatile memory cell having current compensated for temperature dependency and data read method thereof
02/15/2007US20070036015 Semiconductor device temperature sensor and semiconductor storage device
02/15/2007US20070036003 Soft Erasing Methods for Nonvolatile Memory Cells
02/15/2007US20070036002 Programming flash memories
02/15/2007US20070036001 Floating-gate nonvolatile semiconductor memory device
02/15/2007US20070036000 Semiconductor integrated circuit device
02/15/2007US20070035999 Page buffer circuit of flash memory device with dual page program function and program operation method thereof
02/15/2007US20070035998 Nonvolatile memory apparatus
02/15/2007US20070035996 Nonvolatile semiconductor memory device and method of operating the same
02/15/2007US20070035995 Method of programming a four-level flash memory device and a related page buffer
02/15/2007US20070035994 Method and apparatus for programming multi level cell flash memory device
02/15/2007US20070035992 Non-volatile semiconductor memory and method for reading a memory cell
02/15/2007US20070035990 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
02/15/2007US20070035989 Ideal CMOS SRAM system implementation
02/15/2007US20070035988 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device
02/15/2007US20070035987 Static random access memory device having a voltage-controlled word line driver for retain till accessed mode and method of operating the same
02/15/2007US20070035986 SRAM cell using separate read and write circuitry
02/15/2007US20070035985 Voltage controlled static random access memory
02/15/2007US20070035984 A semiconductor device including a memory unit and a logic unit
02/15/2007US20070035983 Ferroelectric random access memory device and method for controlling writing sections therefor
02/15/2007US20070035982 Ferroelectric memory device
02/15/2007US20070035981 Apparatus and method for dynamic control of double gate devices
02/15/2007US20070035980 System and method for optically interconnecting memory devices
02/15/2007US20070035585 Fluid-ejecting integrated circuit utilizing electromagnetic displacement
02/15/2007US20070035583 Nozzle arrangement incorporating a lever based ink displacement mechanism
02/15/2007US20070035582 Inkjet printhead having inkjet nozzle arrangements incorporating dynamic and static nozzle parts
02/15/2007US20070034968 Semiconductor integrated circuit device and a method of manufacturing the same
02/15/2007US20070034935 Nonvolatile semiconductor memory device and a method of the same
02/15/2007DE19963417B4 Nichtflüchtiger ferroelektrischer Speicher Non-volatile ferroelectric memory
02/15/2007DE102006031346A1 Temperaturabhängiges Selbstauffrischmodul für einen Speicherbaustein Temperature-dependent Selbstauffrischmodul for a memory module
02/15/2007DE102006028966A1 Phasenregelkreisschaltung, Verfahren zum Verriegeln der Phase, Speicherbauelement und Speichersystem Phase-locked loop circuit for locking the phase method, memory device and memory system
02/15/2007DE102006024096A1 Verzögerungsregelkreis Delay locked loop
02/14/2007EP1751772A2 Configurable ready/busy control
02/14/2007EP1751771A1 Bitune governed approach for program control of non-volatile memory
02/14/2007EP1751770A1 Boosting to control programming of non-volatile memory
02/14/2007EP1751769A1 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
02/14/2007EP1751768A1 Method and system for controlling refresh in volatile memories
02/14/2007EP1751767A1 Thin film memory device having a variable resistance
02/14/2007EP1751766A1 Digital magnetic current sensor and logic
02/14/2007EP1751765A2 Controllable nanomechanical memory element
02/14/2007EP1751764A1 Spin barrier enhanced dual magnetoresistance effect element and magnetic memory using the same
02/14/2007EP1751762A2 Automatic hidden refresh in a dram and method therefor
02/14/2007EP1634296A4 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
02/14/2007EP1573820B1 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell
02/14/2007EP1550109B1 Storage system using electromagnetic array
02/14/2007EP1108257B1 An mram cell requiring low switching field
02/14/2007CN1914739A NOR-type channel-program channel-erase contactless flash memory on soi
02/14/2007CN1914689A Non-volatile memory and method with control data management
02/14/2007CN1914688A Molecular memory devices and methods
02/14/2007CN1913039A Story device, non-volatile memory device and micro-processing system
02/14/2007CN1913038A Method of controlling refresh operation in multi-port dram and a memory system using the method
02/14/2007CN1913037A 数据记录装置 Data recording means
02/14/2007CN1913036A Semiconductor memory device and a refresh clock signal generator thereof
02/14/2007CN1300851C Semiconductor memory device with signal distributive circuits formed above memory unit
02/14/2007CN1300839C Process for preparing nano electronic phase change storage
02/14/2007CN1300801C Automatic partial-array updating system and method for semiconductor memory
02/14/2007CN1299913C Printing cartridge with an integrated circuit device
02/13/2007US7178004 Memory array programming circuit and a method for using the circuit
02/13/2007US7178001 Semiconductor memory asynchronous pipeline
02/13/2007US7177998 Method, system and memory controller utilizing adjustable read data delay settings
02/13/2007US7177977 Operating non-volatile memory without read disturb limitations
02/13/2007US7177225 Block redundancy implementation in heirarchical RAM'S
02/13/2007US7177224 Controlling multiple signal polarity in a semiconductor device
02/13/2007US7177223 Memory device and method having banks of different sizes