Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2004
12/02/2004WO2004021022A3 Integrated circuit with embedded identification code
12/02/2004WO2003075477A3 High speed configurable transceiver architecture
12/02/2004US20040243966 Modular array defined by standard cell logic
12/02/2004US20040243753 Memory device having programmable drive strength setting
12/02/2004US20040242171 Transmitter circuit, transmission circuit and driver unit
12/02/2004US20040240258 Standard cell arrangement for a magneto-resistive component
12/02/2004US20040240251 Memory device with function to perform operation, and method of performing operation and storage
12/02/2004US20040239662 Simple signal transmission circuit capable of decreasing power consumption
12/02/2004US20040239406 Integrated circuit delivering logic levels at a voltage independent from the mains voltage, with no attached regulator for the power section, and corresponding communication module
12/02/2004US20040239395 Semiconductor chip
12/02/2004US20040239394 Semiconductor integrated circuit device in which operating frequency, supply voltage and substrate bias voltage are controllable to reduce power consumption
12/02/2004US20040239391 Method and structure for dynamic slew-rate control using capacitive elements
12/02/2004US20040239385 Apparatus and method for decreasing the lock time of a lock loop circuit
12/02/2004US20040239382 Output circuit
12/02/2004US20040239380 Driver circuit with low power termination mode
12/02/2004US20040239370 Symmetric differential logic circuits
12/02/2004US20040239368 Method and system for reducing power consumption in digital circuitry using charge redistribution circuits
12/02/2004US20040239367 Data-driven clock gating for a sequential data-capture device
12/02/2004US20040239365 Double data rate flip-flop
12/01/2004EP1481309A1 Low jitter clock for a multi-gigabit transceiver on a field programmable gate array
12/01/2004CN1552124A Level shift circuit, display, and mobile terminal
12/01/2004CN1551504A Apparatus and method for decreasing the lock time of a lock loop circuit
12/01/2004CN1551503A Decoder circuit, light-receiving amplifier circuit and optical adapter
12/01/2004CN1551502A Level shift circuit
12/01/2004CN1551501A Apparatus and method for calibrating resistance/ capacitor filter circuit
12/01/2004CN1551355A 半导体器件 Semiconductor devices
12/01/2004CN1551332A Programmable logic devices with silicon-germanium circuitry and associated methods
12/01/2004CN1551236A 电压发生电路 Voltage generating circuit
12/01/2004CN1551224A Input/output interface of an integrated circuit device
12/01/2004CN1178392C Level conversion circuit
11/2004
11/30/2004US6826741 Flexible I/O routing resources
11/30/2004US6826730 System and method for controlling current in an integrated circuit
11/30/2004US6826635 Input/output pad with mornitoring ability and operation method thereof
11/30/2004US6826390 Receiver, transceiver circuit, signal transmission method, and signal transmission system
11/30/2004US6826112 Low power logic gate
11/30/2004US6826089 Data output driver and data output method for minimizing data output time variations caused by data paterns
11/30/2004US6825707 Current mode logic (CML) circuit concept for a variable delay element
11/30/2004US6825704 Pulse generation circuit enabling its output pulse cycle to be shortened
11/30/2004US6825699 Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit
11/30/2004US6825698 Programmable high speed I/O interface
11/30/2004US6825695 Unified local clock buffer structures
11/30/2004US6825694 Flip-flop circuit for use in electronic devices
11/30/2004US6825692 Input buffer for multiple differential I/O standards
11/30/2004US6825690 Clock tree network in a field programmable gate array
11/30/2004US6825689 Configurable input/output interface for a microcontroller
11/30/2004US6825687 Selective cooling of an integrated circuit for minimizing power loss
11/25/2004WO2004102807A1 Method for stabilizing operation of electronic circuit and its electronic device
11/25/2004WO2004102804A2 Method and apparatus for signal reception using ground termination and/or non-ground termination
11/25/2004WO2004055986A3 Reconfiguration of the programmable logic of an integrated circuit
11/25/2004WO2003081671A3 Logic components from organic field effect transistors
11/25/2004US20040237059 System and method for reducing design cycle time for designing input/output cells
11/25/2004US20040237055 Logic circuit optimizing method, logic circuit optimizing device and logic circuit composing device
11/25/2004US20040236973 Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state
11/25/2004US20040233752 Half-swing line precharge method and apparatus
11/25/2004US20040233749 Data processing apparatus and logical operation apparatus
11/25/2004US20040233736 Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices
11/25/2004US20040233704 Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device
11/25/2004US20040233600 Thermal sensing circuits using bandgap voltage reference generators without trimming circuitry
11/25/2004US20040233190 Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
11/25/2004US20040232974 Voltage generating circuit
11/25/2004US20040232973 Switch circuit
11/25/2004US20040232969 Voltage supply interface circuit
11/25/2004US20040232967 Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
11/25/2004US20040232946 Input circuits including boosted voltages and related methods
11/25/2004US20040232945 Current mode logic driver that employs a level shifting mechanism
11/25/2004US20040232942 Field programmable gate array and microcontroller system-on-a-chip
11/25/2004DE102004019886A1 Integrierte Hochspannungsschaltung A high voltage IC
11/24/2004EP1480112A2 Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state
11/24/2004EP1479166A2 Standard cell arrangement for a magneto-resistive component
11/24/2004EP1479165A1 Floor planning for programmable gate array having embedded fixed logic circuitry
11/24/2004EP1479164A1 Integrated circuit having reduced substrate bounce
11/24/2004EP1479099A2 Methods and systems for reducing power-on failures of integrated circuits
11/24/2004EP1014259B1 A multi-functional arithmetic apparatus with multi-value states
11/24/2004CN1550068A Circuit for improving noise immunity by DV/DT boosting
11/24/2004CN1550067A Controlling signal states and leakage current during a sleep mode
11/24/2004CN1549345A Pipeline control for power management
11/23/2004US6823224 Data processing system having an on-chip background debug system and method therefor
11/23/2004US6822887 Semiconductor circuit device with mitigated load on interconnection line
11/23/2004US6822504 Correction circuit for generating a control signal for correcting a characteristic change of a transistor, a delay circuit using the same, and a ring oscillator circuit using the same
11/23/2004US6822502 Variable impedance circuit
11/23/2004US6822495 System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop
11/23/2004US6822490 Data output circuit for reducing skew of data signal
11/23/2004US6822480 Bi-directional bus level translator
11/23/2004US6822479 I/O buffer power up sequence
11/23/2004US6822478 Data-driven clock gating for a sequential data-capture device
11/23/2004US6822477 Integrated circuit and associated design method using spare gate islands
11/23/2004US6822476 Logic circuit whose power switch is quickly turned on and off
11/23/2004US6822475 Method for contact pad isolation
11/23/2004US6822298 Large current capacity semiconductor device
11/23/2004US6822267 Signal transmission circuit, CMOS semiconductor device, and circuit board
11/23/2004CA2211438C A novel logic family employing two-terminal chalcogenide switches as the logic gates therein
11/18/2004WO2004100377A1 Clamping circuit to counter parasitic coupling
11/18/2004WO2004100376A1 Buffer circuit
11/18/2004WO2004100375A2 Improvements to resonant line drivers
11/18/2004WO2004100357A2 Large gain-bandwith amplifier
11/18/2004WO2004099510A2 Wear assembly for the digging edge of an excavator
11/18/2004WO2004051853A3 Magnetic logic device
11/18/2004US20040230935 Method and Apparatus for Creating Circuit Redundancy in Programmable Logic Devices
11/18/2004US20040230878 Detecting and diagnosing a malfunctioning host coupled to a communications bus
11/18/2004US20040227572 Input buffer circuit having function of canceling offset voltage