Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
11/2005
11/24/2005US20050260798 Method of forming a negative differential resistance device
11/24/2005US20050260785 Gate oxide film structure for a solid state image pick-up device
11/24/2005US20050260783 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
11/24/2005US20050260453 Method for synthesizing nanoscale structures in defined locations
11/24/2005US20050259489 Semiconductor memory device
11/24/2005US20050259488 Erasable and programmable non-volatile cell
11/24/2005US20050259475 Ballistic injection nrom flash memory
11/24/2005US20050259467 Split gate flash memory cell with ballistic injection
11/24/2005US20050259466 Semiconductor memory device with signal lines arranged across memory cell array thereof
11/24/2005US20050259368 Method and apparatus of terminating a high voltage solid state device
11/24/2005US20050259212 Composition for preparing organic insulator
11/24/2005US20050259210 Plane switching mode liquid crystal display device having improved contrast ratio
11/24/2005US20050259171 CCD imaging device and driving method thereof
11/24/2005US20050259067 Liquid crystal display and its driving method
11/24/2005US20050258532 Semiconductor device
11/24/2005US20050258510 Method for fabricating dielectric mixed layers and capacitive element and use thereof
11/24/2005US20050258509 Substrate, semiconductor device, and substrate fabricating method
11/24/2005US20050258508 Semiconductor device with inductors
11/24/2005US20050258506 Arrangement and process for protecting fuses/anti-fuses
11/24/2005US20050258505 Mixed implantation on polysilicon fuse for CMOS technology
11/24/2005US20050258504 Fuse structure for a semiconductor device
11/24/2005US20050258503 Semiconductor device and method for manufacturing the same
11/24/2005US20050258500 Refractory metal-based electrodes for work function setting in semiconductor devices
11/24/2005US20050258499 Resistance-reduced semiconductor device and methods for fabricating the same
11/24/2005US20050258498 Semiconductor device and method for fabricating the same
11/24/2005US20050258497 Semiconductor device
11/24/2005US20050258494 Versatile system for limiting electric field degradation of semiconductor structures
11/24/2005US20050258493 Reverse conducting semiconductor device and a fabrication method thereof
11/24/2005US20050258492 Low-voltage single-layer polysilicon eeprom memory cell
11/24/2005US20050258491 Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides
11/24/2005US20050258488 Serially connected thin film transistors and fabrication methods thereof
11/24/2005US20050258487 TFT, method of manufacturing the TFT, flat panel display having the TFT, and method of manufacturing the flat panel display
11/24/2005US20050258486 Thin film transistor substrate and fabrication method thereof
11/24/2005US20050258485 Silicon on insulator device and method of manufacturing the same
11/24/2005US20050258484 Power composite integrated semiconductor device and manufacturing method thereof
11/24/2005US20050258483 Quasi-vertical power semiconductor device on a composite substrate
11/24/2005US20050258482 Anti-fuse device
11/24/2005US20050258481 Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate
11/24/2005US20050258480 Trench corner effect bidirectional flash memory cell
11/24/2005US20050258479 Trench MOSFET
11/24/2005US20050258478 Semiconductor device
11/24/2005US20050258477 Semiconductor device and method of manufacturing the same
11/24/2005US20050258476 Planarizing method for forming FIN-FET device
11/24/2005US20050258475 Memory device having an electron trapping layer in a high-K dielectric gate stack
11/24/2005US20050258474 Semiconductor device
11/24/2005US20050258473 Semiconductor device of non- volatile memory
11/24/2005US20050258472 Nonvolatile semiconductor memory device for increasing coupling ratio, and of fabrication method thereof
11/24/2005US20050258471 Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices
11/24/2005US20050258470 Gate stack of nanocrystal memory and method for forming same
11/24/2005US20050258468 Dual work function metal gate integration in semiconductor devices
11/24/2005US20050258467 Nano-crystal non-volatile memory device employing oxidation inhibiting and charge storage enhancing layer
11/24/2005US20050258466 Capacitor and light emitting display using the same
11/24/2005US20050258464 Field effect power transistor
11/24/2005US20050258463 Non-volatile semiconductor memory device and process of manufacturing the same
11/24/2005US20050258461 High-voltage LDMOSFET and applications therefor in standard CMOS
11/24/2005US20050258460 Fabrication methods for compressive strained-silicon and transistors using the same
11/24/2005US20050258459 Method for fabricating semiconductor devices having a substrate which includes group III-nitride material
11/24/2005US20050258458 JFET driver circuit and JFET driving method
11/24/2005US20050258457 CMOS imager pixel designs
11/24/2005US20050258456 Memory with integrated programmable controller
11/24/2005US20050258455 Semiconductor component
11/24/2005US20050258454 Silicon carbide semiconductor device and method for manufacturing the same
11/24/2005US20050258453 Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
11/24/2005US20050258452 Semiconductor device and manufacturing method therefor
11/24/2005US20050258451 Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions
11/24/2005US20050258450 Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
11/24/2005US20050258448 Thyristor component with improved blocking capabilities in the reverse direction
11/24/2005US20050258447 Electronic parts and method of manufacturing electronic parts packaging structure
11/24/2005US20050258440 Light emitting diode light source
11/24/2005US20050258439 Light emitting diode light source
11/24/2005US20050258433 Carbene metal complexes as OLED materials
11/24/2005US20050258431 Dielectric passivation for semiconductor devices
11/24/2005US20050258428 Thin-film transistor array with ring geometry
11/24/2005US20050258427 Vertical thin film transistor electronics
11/24/2005US20050258426 Organic light emitting display device
11/24/2005US20050258425 Photoelectric conversion device, image scanning apparatus, and manufacturing method of the photoelectric conversion device
11/24/2005US20050258424 Integrated capacitor
11/24/2005US20050258423 Semiconductor device and electronic device
11/24/2005US20050258422 Thin film transistor and flat panel display using the same
11/24/2005US20050258421 Semiconductor device and manufacture method thereof
11/24/2005US20050258420 Semiconductor device having a gap between a gate electrode and a dummy gate electrode
11/24/2005US20050258419 System and method for making nanoparticles with controlled emission properties
11/24/2005US20050258418 Blue light emitting semiconductor nanocrystal materials
11/24/2005US20050258416 Switching devices based on half-metals
11/24/2005US20050258415 Heterojunction far infrared photodetector
11/24/2005US20050258350 Optoelectronic semiconductor device and method of manufacturing such a device
11/24/2005DE69034191T2 EEPROM-System mit aus mehreren Chips bestehender Blocklöschung EEPROM system with an existing block of several chips deletion
11/24/2005DE102005018347A1 Flash-Speicherzelle, Flash-Speichervorrichtung und Herstellungsverfahren hierfür Flash memory cell flash memory device and manufacturing method thereof
11/24/2005DE102004063454A1 Verfahren zur Herstellung einer Gateelektrode einer Halbleitervorrichtung A method of manufacturing a gate electrode of a semiconductor device
11/24/2005DE102004063452A1 Fabrication of flash memory device includes depositing first oxide layer, polysilicon layers, and dielectric layer, forming second oxide layer, performing heat treatment, and removing parts of dielectric layer and second polysilicon layer
11/24/2005DE102004021457A1 Production of a layer structure for DRAM memory chips comprises depositing an amorphous silicon layer on a substrate using a PECVD method and structuring the silicon layer to form a hard mask
11/24/2005DE102004021391A1 Integrated circuit has cmos and or logic circuit and a power circuit with pile up effect dopant enrichment by the trench structure
11/24/2005DE102004021054A1 Semiconductor component for a flip-chip structure has contact layers between a semiconductor chip and a chip carrier
11/24/2005DE102004021050A1 Field effect semiconductor device, e.g. depletion trench gate FET, has p-type region embedded in n-type semiconductor body near insulating layer and connected to gate electrode
11/24/2005DE102004021041A1 Kombinierter Absolutdruck- und Relativdrucksensor Combined absolute pressure and gauge pressure sensor
11/24/2005DE102004020593A1 Fin-Feldeffekttransistor-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffektransistor-Anordnung Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
11/24/2005DE102004010673A1 Semiconductor device, has two tunnel FETs of opposite conductivity types arranged in substrate
11/24/2005DE10152911B4 Integrierte Schaltungsvorrichtungen, die aktive Bereiche mit erweiterten effektiven Breiten aufweisen, und Verfahren zur Herstellung derselben Integrated circuit devices having active regions with enhanced effective widths, and processes for making them
11/23/2005EP1598860A2 TFT, method of manufacturing the TFT, flat panel display having the TFT, and method of manufacturing the flat panel display
11/23/2005EP1598859A1 Substrate processing method