Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
12/2005
12/08/2005WO2005117132A1 Planar dual gate semiconductor device
12/08/2005WO2005117131A1 Electric device with vertical component
12/08/2005WO2005117130A2 Stepped tip junction with spacer layer
12/08/2005WO2005117129A1 Improved dielectric passivation for semiconductor devices
12/08/2005WO2005117128A1 Tunnel junction barrier layer comprising a diluted semiconductor with spin sensitivity
12/08/2005WO2005117127A1 Quantum device, quantum logic device, method of driving quantum logic device, and logic circuit by quantum logic device
12/08/2005WO2005117126A1 Method for forming fine particle array on substrate and semiconductor element
12/08/2005WO2005117125A2 Yield improvement in silicon-germanium epitaxial growth
12/08/2005WO2005117121A2 Memory arrays; methods of forming memory arrays; and methods of forming contacts to bitlines
12/08/2005WO2005117102A2 Low-voltage single-layer polysilicon eeprom memory cell
12/08/2005WO2005117101A2 Method for making a semiconductor structure using silicon germanium
12/08/2005WO2005117091A1 Method for fabricating semiconductor devices having a substrate which includes group iii-nitride material
12/08/2005WO2005117076A1 Compound semiconductor epitaxial substrate and process for producing the same
12/08/2005WO2005117073A2 Semiconductor device and method for manufacture
12/08/2005WO2005116745A1 Active matrix substrate, method for correcting a pixel deffect therein and manufacturing method thereof
12/08/2005WO2005115911A1 Nanotube position controlling method, nanotube position controlling flow path pattern and electronic element using nanotube
12/08/2005WO2005074451A3 Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
12/08/2005WO2005072154A3 Vertical gate cmos with lithography-independent gate length
12/08/2005WO2005071738A3 Shallow trench isolation process and structure
12/08/2005WO2005067683A3 Inorganic nanowires
12/08/2005WO2004086528A3 Field-effect electrodes for organic, optoelectronic components
12/08/2005US20050273309 Circuit simulation method, device model, and simulation circuit
12/08/2005US20050272341 Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby
12/08/2005US20050272272 Semiconductor device and method for manufacturing the same
12/08/2005US20050272270 Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction
12/08/2005US20050272266 Semiconductor device and its manufacturing method
12/08/2005US20050272262 Methods of manufacturing semiconductor devices
12/08/2005US20050272240 Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors
12/08/2005US20050272239 Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
12/08/2005US20050272235 Method of forming silicided gate structure
12/08/2005US20050272233 Recessed gate electrodes having covered layer interfaces and methods of forming the same
12/08/2005US20050272232 Method for forming gate electrode of semiconductor device
12/08/2005US20050272231 Gate-all-around type of semiconductor device and method of fabricating the same
12/08/2005US20050272230 Complementary analog bipolar transistors with trench-constrained isolation diffusion
12/08/2005US20050272228 Annealing apparatus, annealing method, and manufacturing method of a semiconductor device
12/08/2005US20050272216 Method of making a semiconductor device, and semiconductor device made thereby
12/08/2005US20050272215 Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide
12/08/2005US20050272214 Electrophoretic assembly of electrochemical devices
12/08/2005US20050272212 Method of high precision printing for manufacturing organic thin film transistor
12/08/2005US20050272210 Method for manufacturing gate electrode of semiconductor device using aluminium nitride film
12/08/2005US20050272209 Method of isolating the current sense on power devices while maintaining a continuous stripe cell
12/08/2005US20050272208 Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique
12/08/2005US20050272207 Complementary analog bipolar transistors with trench-constrained isolation diffusion
12/08/2005US20050272206 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
12/08/2005US20050272204 Method for manufacturing NAND flash device
12/08/2005US20050272200 Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film
12/08/2005US20050272199 Method of manufacturing a semiconductor device
12/08/2005US20050272198 Method of manufacturing nonvolatile semiconductor memory device
12/08/2005US20050272196 Method of depositing a higher permittivity dielectric film
12/08/2005US20050272195 Integrated circuit having pairs of parallel complementary finfets
12/08/2005US20050272194 Methods of forming integrated circuit devices including raised source/drain structures having different heights
12/08/2005US20050272193 Method for manufacturing semiconductor device
12/08/2005US20050272192 Methods of forming fin field effect transistors using oxidation barrier layers and related devices
12/08/2005US20050272191 Replacement gate process for making a semiconductor device that includes a metal gate electrode
12/08/2005US20050272190 Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices
12/08/2005US20050272189 Method of manufacturing thin film transistor array panel
12/08/2005US20050272187 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
12/08/2005US20050272186 Method for forming a lightly doped drain in a thin film transistor
12/08/2005US20050272185 Method of fabricating a semiconductor thin film and semiconductor thin film fabrication apparatus
12/08/2005US20050272176 Method for forming LED by a substrate removal process
12/08/2005US20050272170 Method of manufacturing ferroelectric film capacitor
12/08/2005US20050271106 Surface emitting semiconductor laser, its manufacturing method, and manufacturing method of electron device
12/08/2005US20050270869 Transistor
12/08/2005US20050270851 Data processing device
12/08/2005US20050270849 Program/erase method for p-channel charge trapping memory device
12/08/2005US20050270845 Nonvolatile semiconductor memory device and manufacturing method thereof
12/08/2005US20050270824 Nanotube-based switching elements with multiple controls
12/08/2005US20050270757 Electronic devices with small functional elements supported on a carrier
12/08/2005US20050270752 Electronic devices with small functional elements supported on a carrier
12/08/2005US20050270710 Silicon controlled rectifier for the electrostatic discharge protection
12/08/2005US20050270470 Contact structure
12/08/2005US20050270469 Contact structure
12/08/2005US20050270454 Liquid crystal display device and fabricating method thereof
12/08/2005US20050270389 Method and device using CCD-based low noise parametric amplifier
12/08/2005US20050270088 Active phase cancellation for inductor/capacitor networks
12/08/2005US20050270035 Short detection circuit and short detection method
12/08/2005US20050269961 Organic EL display and active matrix substrate
12/08/2005US20050269921 Wire baskets and related devices
12/08/2005US20050269717 Pressure sensitive adhesive sheet for use in semiconductor working and method for producing semiconductor chip
12/08/2005US20050269711 Semiconductor device
12/08/2005US20050269700 Semiconductor component and system having thinned, encapsulated dice
12/08/2005US20050269696 Semiconductor device and manufacturing method of the same
12/08/2005US20050269671 Support for hybrid epitaxy and method of fabrication
12/08/2005US20050269666 Electrical fuses as programmable data storage
12/08/2005US20050269665 Three dimensional integrated circuits
12/08/2005US20050269664 Bipolar transistor with isolation and direct contacts
12/08/2005US20050269663 Semiconductor integrated circuit device and a method of manufacturing the same
12/08/2005US20050269662 Semiconductor device and manufacturing method thereof
12/08/2005US20050269661 Lateral channel transistor
12/08/2005US20050269660 Voltage booster transistor
12/08/2005US20050269658 Structure for realizing integrated circuit having schottky biode and method of fabricating the same
12/08/2005US20050269654 Pressure sensor
12/08/2005US20050269652 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
12/08/2005US20050269651 Method for forming a dielectric stack
12/08/2005US20050269650 Semiconductor device having stress and its manufacture method
12/08/2005US20050269649 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth
12/08/2005US20050269648 Gated field effect devices
12/08/2005US20050269647 Flip chip FET device
12/08/2005US20050269646 Memory
12/08/2005US20050269645 Semiconductor device and method for manufacturing semiconductor device