Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
12/2005
12/15/2005WO2005119764A1 Semiconductor device and method for manufacturing the same
12/15/2005WO2005119762A1 Single metal gate material cmos using strained si-silicon germanium heterojunction layered substrate
12/15/2005WO2005119752A1 Method for forming a semiconductor device having a silicide layer
12/15/2005WO2005119746A1 Separately strained n-channel and p-channel transistors
12/15/2005WO2005119744A1 Method for manufacturing compound semiconductor substrate provided with pn junction
12/15/2005WO2005119743A1 Substrate for electronic application comprising a flexible support and method for production thereof
12/15/2005WO2005119741A2 Dram structures with source/drain pedestals and manufacturing method thereof
12/15/2005WO2005109520A3 Electromechanical electron transfer devices
12/15/2005WO2005091795A3 Method of making a semiconductor device, and semiconductor device made thereby
12/15/2005WO2005091392B1 Micro-reflectors on a substrate for high-density led array
12/15/2005WO2005083794A3 High voltage pmos transistor
12/15/2005WO2005079400A3 Buried guard ring and radiation hardened isolation structures and fabrication methods
12/15/2005WO2005076807A3 A threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same
12/15/2005WO2005074471A3 Method for forming a memory structure using a modified surface topography and structure thereof
12/15/2005WO2005067020A3 A method of varying etch selectivities of a film
12/15/2005WO2005048318A3 Nitride metal oxide semiconductor integrated transistor devices
12/15/2005WO2005043176A3 Probe testing structure
12/15/2005WO2005005562B1 Plasma spraying for joining silicon parts
12/15/2005US20050278673 Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device
12/15/2005US20050277291 Method of manufacturing electronic device
12/15/2005US20050277288 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
12/15/2005US20050277282 Method of manufacturing wiring substrate
12/15/2005US20050277275 Method for forming a semiconductor device having a silicide layer
12/15/2005US20050277271 RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN
12/15/2005US20050277267 Method for manufacturing a compound material wafer
12/15/2005US20050277264 Improved process for forming a buried plate
12/15/2005US20050277261 Method for manufacturing cell transistor
12/15/2005US20050277256 Nanolaminates of hafnium oxide and zirconium oxide
12/15/2005US20050277255 Compound semiconductor device and manufacturing method thereof
12/15/2005US20050277253 Non-volatile memory and method of manufacturing the same
12/15/2005US20050277250 Method for fabricating a floating gate memory device
12/15/2005US20050277249 Methods for forming semiconductor structures
12/15/2005US20050277243 Flash memory having a high-permittivity tunnel dielectric
12/15/2005US20050277238 Method of manufacturing a semiconductor device
12/15/2005US20050277237 Structure from which an integrated circuit may be fabricated and a method of making same
12/15/2005US20050277234 Flexible carbon-based ohmic contacts for organic transistors
12/15/2005US20050277233 Semiconductor device and method of manufacturing the same
12/15/2005US20050277232 Diode junction poly fuse
12/15/2005US20050277217 Method for manufacturing micro-structural unit
12/15/2005US20050277028 Laser apparatus, laser irradiation method, manufacturing method for semiconductor device, semiconductor device, production system for semiconductor device using the laser apparatus, and electronic equipment
12/15/2005US20050276912 Wiring substrate, semiconductor device and manufacturing method thereof
12/15/2005US20050276149 Method of manipulating a quantum system comprising a magnetic moment
12/15/2005US20050276117 Ballistic direct injection flash memory cell on strained silicon structures
12/15/2005US20050276115 Manufacturing method of semiconductor device
12/15/2005US20050276101 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
12/15/2005US20050276090 Nonvolatile magnetic memory device and photomask
12/15/2005US20050276000 Solid state turbine engine ignition exciter having elevated temperature operational capabiltiy
12/15/2005US20050275116 Reconstructed semiconductor wafers
12/15/2005US20050275115 Semiconductor device, circuit substrate, electro-optic device and electronic appliance
12/15/2005US20050275114 Semiconductor device and semiconductor apparatus
12/15/2005US20050275112 High power MCM package with improved planarity and heat dissipation
12/15/2005US20050275108 Semiconductor device and method for fabricating the same
12/15/2005US20050275106 Electronic isolation device
12/15/2005US20050275102 Semiconductor device with low contact resistance and method for fabricating the same
12/15/2005US20050275098 Lead-free conductive jointing bump
12/15/2005US20050275097 Method of forming a solder bump and the structure thereof
12/15/2005US20050275095 Stress mitigation layer to reduce under bump stress concentration
12/15/2005US20050275070 Electrostatic discharge mitigation structure and methods thereof using a dissipative capacitor with voltage dependent resistive material
12/15/2005US20050275066 System and method to reduce noise in a substrate
12/15/2005US20050275065 Diode with improved energy impulse rating
12/15/2005US20050275064 System and method for forming a bipolar switching PCMO film
12/15/2005US20050275063 Semiconductor device
12/15/2005US20050275062 Semiconductor bare chip, method of recording ID information thereon, and method of identifying the same
12/15/2005US20050275060 Structure and method to preserve STI during etching
12/15/2005US20050275059 Isolation trench arrangement
12/15/2005US20050275058 Method for enhancing field oxide and integrated circuit with enhanced field oxide
12/15/2005US20050275057 Schottky diode with dielectric isolation
12/15/2005US20050275054 Autonomic thermal monitor and controller for thin film devices
12/15/2005US20050275052 Imaging sensor
12/15/2005US20050275047 Stress wave sensor
12/15/2005US20050275045 Low capacitance fet for operation at subthreshold voltages
12/15/2005US20050275044 System and device including a barrier alayer
12/15/2005US20050275043 Novel semiconductor device design
12/15/2005US20050275042 Semiconductor device including a field effect transistor and method of forming thereof
12/15/2005US20050275041 Semiconductor device and its manufacturing method
12/15/2005US20050275040 Back gate finfet sram
12/15/2005US20050275039 Semiconductor device and method of manufacturing the same
12/15/2005US20050275038 Indium oxide-based thin film transistors and circuits
12/15/2005US20050275037 Semiconductor devices with high voltage tolerance
12/15/2005US20050275035 Gate Electrode Architecture for Improved Work Function Tuning and Method of Manufacture
12/15/2005US20050275034 A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
12/15/2005US20050275033 Schottky barrier source/drain N-MOSFET using ytterbium silicide
12/15/2005US20050275032 MOS type semiconductor device having electrostatic discharge protection arrangement
12/15/2005US20050275030 Semiconductor device and method of manufacturing the same
12/15/2005US20050275026 MOSFET parametric amplifier
12/15/2005US20050275025 Semiconductor component and method for its production
12/15/2005US20050275023 Semiconductor device and method of manufacturing same
12/15/2005US20050275022 Depletion-merged FET design in bulk silicon
12/15/2005US20050275021 Semiconductor device
12/15/2005US20050275020 Method of forming active device on substrate and the substrate
12/15/2005US20050275019 Thin film transistor and method of fabricating the same
12/15/2005US20050275017 Separately strained N-channel and P-channel transistors
12/15/2005US20050275016 Deep trench super switch device
12/15/2005US20050275015 Method and structure for providing tuned leakage current in cmos integrated circuit
12/15/2005US20050275014 Integration method of a semiconductor device having a recessed gate electrode
12/15/2005US20050275013 Power semiconductor with functional element guide structure
12/15/2005US20050275012 Nonvolatile semiconductor memory device and method of manufacturing the same
12/15/2005US20050275011 NROM flash memory with a high-permittivity gate dielectric
12/15/2005US20050275010 Semiconductor nano-wire devices and methods of fabrication
12/15/2005US20050275009 Nonvolatile memory device
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