Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2005
11/24/2005WO2005112078A1 METHOD FOR MATERIAL GROWTH OF GaN-BASED NITRIDE LAYER
11/24/2005WO2005112077A1 Development apparatus and development method
11/24/2005WO2005112045A1 Dielectric material
11/24/2005WO2005112020A1 Method for producing a multilayer storage media
11/24/2005WO2005111972A1 Display, and method for fabricating same
11/24/2005WO2005111817A2 Semiconductor device and method of forming the same
11/24/2005WO2005111724A1 Antireflective film-forming composition containing vinyl ether compound
11/24/2005WO2005111632A1 Sheet-like probe, method of producing the probe, and application of the probe
11/24/2005WO2005111278A1 Group iii nitride semiconductor crystal, method for producing same, and group iii nitride semiconductor device
11/24/2005WO2005111266A1 Susceptor for vapor deposition apparatus
11/24/2005WO2005111265A1 Method and system of dry cleaning a processing chamber
11/24/2005WO2005111169A1 Connecting material
11/24/2005WO2005110912A1 Tap unit for a beverage dispenser
11/24/2005WO2005110679A1 Composition for polishing
11/24/2005WO2005110666A1 Methods of drilling through-holes in homogeneous and non-homogeneous substrates
11/24/2005WO2005110662A1 Laser machining of a workpiece
11/24/2005WO2005110661A2 Laser thermal processing with laser diode radiation
11/24/2005WO2005110057A2 Crystallographic alignment of high-density nanowire arrays
11/24/2005WO2005094515A3 Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits
11/24/2005WO2005093813A8 Method for manufacturing thin film transistor
11/24/2005WO2005091974A9 Methods for the optimization of substrate etching in a plasma processing system
11/24/2005WO2005091370A8 Method for manufacturing integrated circuit
11/24/2005WO2005088704A8 Semiconductor device
11/24/2005WO2005081798A3 Twin eeprom memory transistors with subsurface stepped floating gates
11/24/2005WO2005081313A3 A microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
11/24/2005WO2005077549A8 Thin film transistor and display device, and method for manufacturing thereof
11/24/2005WO2005069344A3 Gas distribution plate assembly for plasma reactors
11/24/2005WO2005062905A3 Laser lift-off of sapphire from a nitride flip-chip
11/24/2005WO2005062345A3 A method of forming a silicon oxynitride layer
11/24/2005WO2005048322A3 Method and apparatus for improved baffle plate
11/24/2005WO2005043696A3 Laser thermal annealing of lightly doped silicon substrates
11/24/2005WO2005036594A3 Method and apparatus for efficient temperature control using a contact volume
11/24/2005WO2005010994A1 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
11/24/2005WO2005001840A3 Mirror image non-volatile memory cell transistor pairs with single poly layer
11/24/2005WO2004091838A3 Method of soldering or brazing articles having surfaces that are difficult to bond
11/24/2005WO2004056699A3 Nanoparticles, nanoscopic structures and method for production thereof
11/24/2005US20050262468 Designing method and device for phase shift mask
11/24/2005US20050262463 Wiring optimizations for power
11/24/2005US20050262460 Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool
11/24/2005US20050262422 Semiconductor memory device for build-in fault diagnosis
11/24/2005US20050262293 SRAM core cell for light-emitting display
11/24/2005US20050261397 Epoxy resin composition for optical semiconductor element encapsulation and optical semiconductor device which uses the same
11/24/2005US20050261151 Corrosion-inhibiting cleaning compositions for metal layers and patterns on semiconductor substrates
11/24/2005US20050261150 Reactive fluid systems for removing deposition materials and methods for using same
11/24/2005US20050260942 Chemical mechanical polishing pad
11/24/2005US20050260933 Polishing apparatus and method
11/24/2005US20050260928 Integral polishing pad and manufacturing method thereof
11/24/2005US20050260925 Polishing apparatus
11/24/2005US20050260868 Test apparatus having intermediate connection board for package
11/24/2005US20050260864 Method of depositing low k films
11/24/2005US20050260863 Method for fabricating a semiconductor device
11/24/2005US20050260862 Semiconductor device and method for producing the same
11/24/2005US20050260861 Method for evaluating semiconductor substrate
11/24/2005US20050260860 Method of pattering a photoresist film using a lithographic
11/24/2005US20050260859 Method for patterning a semiconductor region
11/24/2005US20050260858 Versatile system for limiting electric field degradation of semiconductor structures
11/24/2005US20050260857 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma
11/24/2005US20050260856 Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution
11/24/2005US20050260855 Method and apparatus for planarizing a semiconductor wafer
11/24/2005US20050260854 Atomic layer deposition methods
11/24/2005US20050260853 Surface treatment of copper to improve interconnect formation
11/24/2005US20050260852 Bimetal layer manufacturing method
11/24/2005US20050260851 Barrier metal re-distribution process for resistivity reduction
11/24/2005US20050260850 Low-carbon-doped silicon oxide film and damascene structure using same
11/24/2005US20050260849 Top layers of metal for high performance IC's
11/24/2005US20050260848 Method of forming a recessed structure employing a reverse tone process
11/24/2005US20050260847 Method for forming contact window
11/24/2005US20050260846 Substrate processing method, semiconductor device production method, and semiconductor device
11/24/2005US20050260845 Low-K dielectric etch process for dual-damascene structures
11/24/2005US20050260844 Package with barrier wall and method for manufacturing the same
11/24/2005US20050260843 Device and method to eliminate shorting induced by via to metal misalignment
11/24/2005US20050260842 Final passivation scheme for integrated circuits
11/24/2005US20050260841 Integration scheme for using silicided dual work function metal gates
11/24/2005US20050260840 Method of fabricating T-shaped polysilicon gate by using dual damascene process
11/24/2005US20050260839 Non-volatile resistance switching memory
11/24/2005US20050260838 Methods and systems for dopant profiling
11/24/2005US20050260837 Methods for stable and repeatable ion implantation
11/24/2005US20050260836 Method to overcome instability of ultra-shallow semiconductor junctions
11/24/2005US20050260835 Sheet type heat treating device and method for processing semiconductors
11/24/2005US20050260834 Method for forming a semiconductor
11/24/2005US20050260833 Constant emissivity deposition member
11/24/2005US20050260832 Polycrystalline SiGe junctions for advanced devices
11/24/2005US20050260831 Method and apparatus for forming deposited film
11/24/2005US20050260830 Methods of fabricating a semiconductor device using a dilute aqueous solution of an ammonia and peroxide mixture
11/24/2005US20050260829 Manufacturing method of a semiconductor device
11/24/2005US20050260828 Bonding method, bonding apparatus and sealing means
11/24/2005US20050260827 Ozone vapor clean method
11/24/2005US20050260826 Yield improvement in silicon-germanium epitaxial growth
11/24/2005US20050260825 Shallow trench isolation structure for strained Si on SiGe
11/24/2005US20050260824 Semiconductor device manufacturing method and manufacturing line thereof
11/24/2005US20050260823 Methods and apparatus for forming rhodium-containing layers
11/24/2005US20050260822 Method of manufacturing semiconductor device
11/24/2005US20050260821 Method of fabricating self-aligned silicon carbide semiconductor devices
11/24/2005US20050260820 Method of manufacturing a semiconductor integrated circuit device having a trench
11/24/2005US20050260819 Reduced dielectric constant spacer materials integration for high speed logic gates
11/24/2005US20050260818 Semiconductor device and method for fabricating the same
11/24/2005US20050260817 Semiconductor device and method for manufacturing the same
11/24/2005US20050260816 Method for removing a semiconductor layer
11/24/2005US20050260815 Step gate electrode structures for field-effect transistors and methods for fabricating the same
11/24/2005US20050260814 Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same