Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2005
11/17/2005US20050256687 Generation of a library of periodic grating diffraction signals
11/17/2005US20050256669 Measurement system and method and computer program for processing measurement data
11/17/2005US20050256653 Inter-process sensing of wafer outcome
11/17/2005US20050256600 Electron beam lithography system, method of electron beam lithography, program and method for manufacturing a semiconductor device with direct writing
11/17/2005US20050256599 System and method thereof for real-time batch dispatching manufacturing process
11/17/2005US20050255796 Probe cleaning sheet and cleaning method
11/17/2005US20050255795 Method and system for deflashing mold compound
11/17/2005US20050255717 Method of operating substrate processing device
11/17/2005US20050255716 Laser irradiation method and method for manufacturing semiconductor device using the same
11/17/2005US20050255715 Manufacturing method of composite sheet material using ultrafast laser pulses
11/17/2005US20050255714 Method for silicon nitride chemical vapor deposition
11/17/2005US20050255713 Method and apparatus for forming nitrided silicon film
11/17/2005US20050255712 Method of cvd for forming silicon nitride film on substrate
11/17/2005US20050255711 Method for forming underlying insulation film
11/17/2005US20050255710 Porous materials
11/17/2005US20050255709 Method for manufacturing semiconductor device
11/17/2005US20050255708 Thick film dielectric structure for thick dielectric electroluminescent displays
11/17/2005US20050255706 Method for manufacturing semiconductor device
11/17/2005US20050255705 Prevention of electrostatic wafer sticking in plasma deposition/etch tools
11/17/2005US20050255704 Stacked dielectric layer suppressing electrostatic charge buildup and method of fabricating the same
11/17/2005US20050255703 Dual damascene etching process
11/17/2005US20050255702 Methods of processing a semiconductor substrate
11/17/2005US20050255701 Methods of forming semiconductor constructions
11/17/2005US20050255700 Controlled multi-step magnetron sputtering process
11/17/2005US20050255699 Method for controlling voiding and bridging in silicide formation
11/17/2005US20050255698 Chemical vapor deposition of titanim
11/17/2005US20050255697 Selective etching of organosilicate films over silicon oxide stop etch layers
11/17/2005US20050255696 Method of processing resist, semiconductor device, and method of producing the same
11/17/2005US20050255695 Decreasing the residue of a silicon dioxide layer after trench etching
11/17/2005US20050255694 Hardening of copper to improve copper CMP performance
11/17/2005US20050255693 Passivative chemical mechanical polishing composition for copper film planarization
11/17/2005US20050255692 Adhering layers to metals with dielectric adhesive layers
11/17/2005US20050255691 Self-ionized and inductively-coupled plasma for sputtering and resputtering
11/17/2005US20050255690 Multi-step barrier deposition method
11/17/2005US20050255689 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
11/17/2005US20050255688 Semiconductor device and manufacturing method thereof, electro-optical device and manufacturing method thereof, and electronic apparatus
11/17/2005US20050255687 Plasma treatment for silicon-based dielectrics
11/17/2005US20050255686 Method of manufacturing semiconductor device
11/17/2005US20050255685 Void free solder arrangement for screen printing semiconductor wafers
11/17/2005US20050255684 Implantation of deuterium in MOS and DRAM devices
11/17/2005US20050255683 Implant optimization scheme
11/17/2005US20050255682 Process for transferring a layer of strained semiconductor material
11/17/2005US20050255681 Method of forming pre-metal dielectric layer
11/17/2005US20050255679 Thin film semiconductor device
11/17/2005US20050255678 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
11/17/2005US20050255677 Integrated circuit with impurity barrier
11/17/2005US20050255676 Configuring a performance state of an integrated circuit die on wafer
11/17/2005US20050255675 Apparatus for supporting wafers for die singulation and subsequent handling and in-process wafer structure
11/17/2005US20050255674 Semiconductor device including semiconductor memory element and method for producing same
11/17/2005US20050255673 Apparatus and method for semicondutor chip detachment
11/17/2005US20050255672 Method and resulting structure for manufacturing semiconductor substrates
11/17/2005US20050255671 Process for producing silicon on insulator structure having intrinsic gettering by ion implantation
11/17/2005US20050255670 Glass-based SOI structures
11/17/2005US20050255669 Semiconductor device including isolation trench and method for fabricating the same
11/17/2005US20050255668 Method of fabricating shallow trench isolation structure
11/17/2005US20050255667 Method of inducing stresses in the channel region of a transistor
11/17/2005US20050255666 Method and structure for aligning mechanical based device to integrated circuits
11/17/2005US20050255665 Manufacturing method of a contact structure and phase change memory cell with elimination of double contacts
11/17/2005US20050255664 Method of forming a metal-insulator-metal capacitor
11/17/2005US20050255663 Semiconductor device and method of manufacturing the same
11/17/2005US20050255662 Semiconductor device with load resistor and fabrication method
11/17/2005US20050255661 Semiconductor device and manufacturing method therefor
11/17/2005US20050255660 Ion implantation method for forming a shallow junction
11/17/2005US20050255659 CMOS transistor using high stress liner layer
11/17/2005US20050255658 Flash memory cell and manufacturing method thereof
11/17/2005US20050255657 Methods of forming a nonvolatile memory device having a local SONOS structure that use spacers to adjust the overlap between a gate electrode and a charge trapping layer
11/17/2005US20050255656 Field effect transistor (FET) devices and methods of manufacturing FET devices
11/17/2005US20050255655 N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects
11/17/2005US20050255654 Methods of forming non-volatile memory devices having floating gate electrodes
11/17/2005US20050255653 Integrated circuit devices having uniform silicide junctions
11/17/2005US20050255652 Semiconductor device and method of producing the same
11/17/2005US20050255651 Bitline implant utilizing dual poly
11/17/2005US20050255650 Semiconductor device
11/17/2005US20050255649 Method of fabricating heterojunction devices integrated with CMOS
11/17/2005US20050255648 Silicon based substrate hafnium oxide top environmental/thermal top barrier layer and method for preparing
11/17/2005US20050255647 Vertical NROM having a storage density of 1 bit per 1F2
11/17/2005US20050255646 Heatsink device and method
11/17/2005US20050255645 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
11/17/2005US20050255644 Semiconductor device having both memory and logic circuit and its manufacture
11/17/2005US20050255643 Method of forming fin field effect transistor using damascene process
11/17/2005US20050255642 Method of fabricating inlaid structure
11/17/2005US20050255641 Semiconductor device and method of manufacturing the same
11/17/2005US20050255640 Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidification
11/17/2005US20050255639 Complementary thin film transistor circuit, electro-optical device, and electronic apparatus
11/17/2005US20050255638 Trench corner effect bidirectional flash memory cell
11/17/2005US20050255637 Method for assembling semiconductor die packages with standard ball grid array footprint
11/17/2005US20050255636 Microtools for package substrate patterning
11/17/2005US20050255635 Microelectronic assembly having a thermally conductive member with a cavity to contain a portion of a thermal interface material
11/17/2005US20050255634 Chemical-enhanced package singulation process
11/17/2005US20050255633 Methods for producing an electronic device having microscopically small contact areas
11/17/2005US20050255632 Method of fabricating stacked semiconductor device
11/17/2005US20050255630 Method and apparatus for manufacturing a packaged semiconductor device, packaged semiconductor device obtained with such a method and metal carrier suitable for use in such a method
11/17/2005US20050255629 Biomimetic approach to low-cost fabrication of complex nanostructures of metal oxides by natural oxidation at low-temperature
11/17/2005US20050255628 Microelectronic devices and methods for packaging microelectronic devices
11/17/2005US20050255626 Method of manufacturing semiconductor device
11/17/2005US20050255625 Image sensor with deep well region and method of fabricating the image sensor
11/17/2005US20050255624 Positioning apparatus, exposure apparatus, and device manufacturing method
11/17/2005US20050255623 Method of manufacturing liquid crystal display
11/17/2005US20050255622 Substrate, liquid crystal display having the substrate, and method for producing substrate
11/17/2005US20050255621 Thin film transistor device and method of manufacturing the same
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