| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/24/2015 | US8962492 Method to thin a silicon-on-insulator substrate |
| 02/24/2015 | US8962491 Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby |
| 02/24/2015 | US8962490 Method for fabricating semiconductor device |
| 02/24/2015 | US8962489 Method for etching film containing cobalt and palladium |
| 02/24/2015 | US8962488 Synchronized radio frequency pulsing for plasma etching |
| 02/24/2015 | US8962487 Method for making microchannels on a substrate, and substrate including such microchannels |
| 02/24/2015 | US8962486 Method of forming opening on semiconductor substrate |
| 02/24/2015 | US8962485 Reusing active area mask for trench transfer exposure |
| 02/24/2015 | US8962484 Method of forming pattern for semiconductor device |
| 02/24/2015 | US8962483 Interconnection designs using sidewall image transfer (SIT) |
| 02/24/2015 | US8962482 Multi-layer interconnect with isolation layer |
| 02/24/2015 | US8962481 Chip-on-wafer structures and methods for forming the same |
| 02/24/2015 | US8962480 ESD network circuit with a through wafer via structure and a method of manufacture |
| 02/24/2015 | US8962479 Interconnect structures containing nitrided metallic residues |
| 02/24/2015 | US8962478 Method to use self-repair Cu barrier to solve barrier degradation due to Ru CMP |
| 02/24/2015 | US8962477 High temperature anneal for stress modulation |
| 02/24/2015 | US8962476 Method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis |
| 02/24/2015 | US8962475 Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density |
| 02/24/2015 | US8962474 Method for forming an air gap around a through-silicon via |
| 02/24/2015 | US8962473 Method of forming hybrid diffusion barrier layer and semiconductor device thereof |
| 02/24/2015 | US8962472 Semiconductor device with self-aligned air gap and method for fabricating the same |
| 02/24/2015 | US8962471 Bump, method for forming the bump, and method for mounting substrate having the bump thereon |
| 02/24/2015 | US8962470 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus |
| 02/24/2015 | US8962469 Methods of stripping resist after metal deposition |
| 02/24/2015 | US8962468 Formation of ohmic contacts on wide band gap semiconductors |
| 02/24/2015 | US8962467 Metal fuse structure for improved programming capability |
| 02/24/2015 | US8962466 Low temperature transition metal oxide for memory device |
| 02/24/2015 | US8962465 Methods of forming gated devices |
| 02/24/2015 | US8962464 Self-alignment for using two or more layers and methods of forming same |
| 02/24/2015 | US8962463 Semiconductor device with dual work function gate stacks and method for fabricating the same |
| 02/24/2015 | US8962462 Overvoltage tolerant HFETs |
| 02/24/2015 | US8962461 GaN HEMTs and GaN diodes |
| 02/24/2015 | US8962460 Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide materials, and methods of forming semiconductor device structures including same |
| 02/24/2015 | US8962459 Diffusion sources from liquid precursors |
| 02/24/2015 | US8962458 Methods of growing nitride semiconductors and methods of manufacturing nitride semiconductor substrates |
| 02/24/2015 | US8962457 Insulated gate type transistor and display device |
| 02/24/2015 | US8962456 Group III nitride semiconductor single crystal, method for producing the same, self-standing substrate, and semiconductor device |
| 02/24/2015 | US8962455 Method of fabricating semiconductor device |
| 02/24/2015 | US8962454 Method of depositing dielectric films using microwave plasma |
| 02/24/2015 | US8962453 Single crystal growth on a mis-matched substrate |
| 02/24/2015 | US8962452 Semiconductor die singulation apparatus and method |
| 02/24/2015 | US8962451 Wafer processing method |
| 02/24/2015 | US8962450 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses |
| 02/24/2015 | US8962449 Methods for processing semiconductor devices |
| 02/24/2015 | US8962448 Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier |
| 02/24/2015 | US8962447 Bonded strained semiconductor with a desired surface orientation and conductance direction |
| 02/24/2015 | US8962446 Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions |
| 02/24/2015 | US8962445 Method of manufacture of semiconductor isolation structure |
| 02/24/2015 | US8962444 Semiconductor device and method of manufacturing the same |
| 02/24/2015 | US8962443 Semiconductor device having an airbridge and method of fabricating the same |
| 02/24/2015 | US8962442 Janus complementary MEMS transistors and circuits |
| 02/24/2015 | US8962441 Transistor device with improved source/drain junction architecture and methods of making such a device |
| 02/24/2015 | US8962440 Semiconductor device and method of manufacturing semiconductor device |
| 02/24/2015 | US8962439 Memory cell |
| 02/24/2015 | US8962437 Method for fabricating capacitor with high aspect ratio |
| 02/24/2015 | US8962436 Lateral bipolar transistors having partially-depleted intrinsic base |
| 02/24/2015 | US8962435 Method of forming semiconductor device having embedded strain-inducing pattern |
| 02/24/2015 | US8962434 Field effect transistors with varying threshold voltages |
| 02/24/2015 | US8962433 MOS transistor process |
| 02/24/2015 | US8962432 Semiconductor device with self aligned end-to-end conductive line structure and method for forming the same |
| 02/24/2015 | US8962431 Methods of forming metal silicide-comprising material and methods of forming metal silicide-comprising contacts |
| 02/24/2015 | US8962430 Method for the formation of a protective dual liner for a shallow trench isolation structure |
| 02/24/2015 | US8962429 Integrated circuits with improved spacers and methods for fabricating same |
| 02/24/2015 | US8962428 Method of manufacturing a semiconductor device |
| 02/24/2015 | US8962427 Method of producing semiconductor device |
| 02/24/2015 | US8962426 Method of manufacture for a semiconductor device |
| 02/24/2015 | US8962425 Semiconductor device and method of forming junction enhanced trench power MOSFET having gate structure embedded within trench |
| 02/24/2015 | US8962424 N-type silicon solar cell with contact/protection structures |
| 02/24/2015 | US8962423 Multilayer MIM capacitor |
| 02/24/2015 | US8962422 Method of fabricating semiconductor devices |
| 02/24/2015 | US8962421 Methods for fabricating integrated circuits including semiconductive resistor structures in a FinFET architecture |
| 02/24/2015 | US8962420 Semiconductor device comprising a buried poly resistor |
| 02/24/2015 | US8962419 Complementary stress memorization technique layer method |
| 02/24/2015 | US8962418 Manufacturing method of semiconductor device having semiconductor layers with different thicknesses |
| 02/24/2015 | US8962417 Method and structure for pFET junction profile with SiGe channel |
| 02/24/2015 | US8962416 Split gate non-volatile memory cell |
| 02/24/2015 | US8962415 Methods of forming gates of semiconductor devices |
| 02/24/2015 | US8962414 Reduced spacer thickness in semiconductor device fabrication |
| 02/24/2015 | US8962413 Methods of forming spacers on FinFETs and other semiconductor devices |
| 02/24/2015 | US8962412 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same |
| 02/24/2015 | US8962411 Circuit pattern with high aspect ratio and method of manufacturing the same |
| 02/24/2015 | US8962410 Transistors with different threshold voltages |
| 02/24/2015 | US8962409 Semiconductor device and fabrication method |
| 02/24/2015 | US8962408 Replacement gate self-aligned carbon nanostructure transistor |
| 02/24/2015 | US8962407 Method and device to achieve self-stop and precise gate height |
| 02/24/2015 | US8962406 Flatband shift for improved transistor performance |
| 02/24/2015 | US8962405 Method of manufacturing semiconductor device by mounting and positioning a semiconductor die using detection marks |
| 02/24/2015 | US8962404 Method for manufacturing fan-out lines on array substrate |
| 02/24/2015 | US8962403 Manufacturing method for switch and array substrate using etching solution comprising amine |
| 02/24/2015 | US8962402 Lateral diffusion metal oxide semiconductor (LDMOS) device with tapered drift electrode |
| 02/24/2015 | US8962401 Double gated 4F2 dram CHC cell and methods of fabricating the same |
| 02/24/2015 | US8962400 In-situ doping of arsenic for source and drain epitaxy |
| 02/24/2015 | US8962399 Method of making a semiconductor layer having at least two different thicknesses |
| 02/24/2015 | US8962398 Body contacted hybrid surface semiconductor-on-insulator devices |
| 02/24/2015 | US8962397 Multiple well drain engineering for HV MOS devices |
| 02/24/2015 | US8962396 Fabrication method of carrier-free semiconductor package |
| 02/24/2015 | US8962395 QFN package and manufacturing process thereof |
| 02/24/2015 | US8962394 Semiconductor device and method of manufacturing the same |
| 02/24/2015 | US8962393 Integrated circuit packaging system with heat shield and method of manufacture thereof |
| 02/24/2015 | US8962392 Underfill curing method using carrier |