Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
06/1998
06/24/1998CN1038884C Circuit for controlling self-refresh period in semiconductor memory device
06/23/1998US5771369 Memory row redrive
06/23/1998US5771346 Apparatus and method for detecting over-programming condition in multistate memory device
06/23/1998US5771208 Memory for storing multi-data
06/23/1998US5771201 Synchronous semiconductor device having an apparatus for producing strobe clock signals
06/23/1998US5771200 Semiconductor memory device
06/23/1998US5771199 Integrated circuit memory devices having improved dual memory bank control capability and methods of operating same
06/23/1998US5771198 Source voltage generating circuit in semiconductor memory
06/23/1998US5771195 Circuit and method for replacing a defective memory cell with a redundant memory cell
06/23/1998US5771190 Semiconductor static random access memory device having memory cells coupled to discharging line different in potential level to discharging line for write-in circuit
06/23/1998US5771189 DRAM cell and method of reading data from DRAM cell
06/23/1998US5771188 Adjustable cell plate generator
06/23/1998US5771187 Multiple level storage DRAM cell
06/23/1998US5770957 Signal generator for generating sense amplifier enable signal
06/23/1998US5770953 Destructive read sense-amp
06/18/1998WO1998026422A1 Method and apparatus for initializing semiconductor memory
06/17/1998EP0848484A2 Circuit for generating a boosted output voltage
06/17/1998EP0847583A1 Electrically programmable memory, method of programming and method of reading
06/17/1998EP0847582A1 Memory system having programmable control parameters
06/17/1998EP0847581A1 Expandable data width sam for a multiport ram
06/17/1998EP0813705A4 High precision voltage regulation circuit for programming multilevel flash memory
06/17/1998CN1184971A 虚拟通道存储器系统 Virtual channel memory system
06/16/1998USRE35825 Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
06/16/1998US5768290 Semiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail determination method thereof
06/16/1998US5768287 Apparatus and method for programming multistate memory device
06/16/1998US5768214 Semiconductor memory device
06/16/1998US5768213 Clock generating circuit for use in semiconductor memory device
06/16/1998US5768212 Semiconductor memory
06/16/1998US5768210 Semiconductor memory device
06/16/1998US5768209 Semiconductor memory with NAND type memory cells having NOR gate operation delay means
06/16/1998US5768204 Semiconductor memory device having dummy word lines and method for controlling the same
06/16/1998US5768203 Single-chip memory system having a page access mode
06/16/1998US5768202 Fast sense amplifier for small voltage differences
06/16/1998US5768201 Bit line sense amplifier array for semiconductor memory device
06/16/1998US5768200 Charging a sense amplifier
06/16/1998US5768199 Semiconductor memory device with dual precharge operations
06/16/1998US5768198 Semiconductor memory having redundancy function in block write operation
06/16/1998US5768197 Redundancy circuit for semiconductor memory device
06/16/1998US5768193 Bit-refreshable method and circuit for refreshing a nonvolatile flash memory
06/16/1998US5768192 Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
06/16/1998US5768191 Methods of programming multi-state integrated circuit memory devices
06/16/1998US5768188 Multi-state non-volatile semiconductor memory and method for driving the same
06/16/1998US5768187 Non-volatile multi-state memory device capable with variable storing resolution
06/16/1998US5768185 Non-volatile semiconductor memory of a metal ferroelectric field effect transistor
06/16/1998US5768184 Performance non-volatile semiconductor memory device
06/16/1998US5768183 Multi-layer magnetic memory cells with improved switching characteristics
06/16/1998US5768181 Magnetic device having multi-layer with insulating and conductive layers
06/16/1998US5768180 Magnetoresistive memory using large fractions of memory cell films for data storage
06/16/1998US5768179 Antifuse load sram cell
06/16/1998US5768178 Data transfer circuit in a memory device
06/16/1998US5768177 Controlled delay circuit for use in synchronized semiconductor memory
06/16/1998US5768176 Method of controlling non-volatile ferroelectric memory cell for inducing a large amount of electric charge representative of data bit
06/16/1998US5768175 Ferroelectric memory with fault recovery circuits
06/16/1998US5768174 Integrated circuit memory devices having metal straps to improve word line driver reliability
06/16/1998US5768173 Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices
06/16/1998US5767735 Variable stage charge pump
06/16/1998US5767700 Pulse signal transfer unit employing post charge logic
06/16/1998US5766985 Process for encapsulating a semiconductor device having a heat sink
06/11/1998WO1998025345A1 Clock vernier adjustment
06/11/1998WO1998025272A1 Precision sense amplifiers and memories, systems and methods using the same
06/11/1998WO1998025271A1 Semiconductor integrated circuit device
06/11/1998WO1998025270A1 Digital step generators and circuits, systems and methods using the same
06/11/1998WO1998025263A1 Lateral magneto-electronic device exploiting a quasi-two-dimensional electron gas
06/10/1998EP0847086A2 Improvements in or relating to semiconductor devices
06/10/1998EP0847059A2 Semiconductor memory
06/10/1998EP0847058A2 Improvements in or relating to integrated circuits
06/10/1998EP0847010A2 Row redundancy block architecture
06/10/1998EP0846343A1 Electrically erasable memory elements characterized by reduced current and improved thermal stability
06/10/1998EP0846326A1 Charge transfer sense amplifier
06/10/1998EP0846325A1 Reduced area sense amplifier isolation layout in a dynamic ram architecture
06/10/1998EP0846324A1 Integrated circuit memory with back end mode disable
06/10/1998EP0846289A1 Field programmable gate array with distributed ram and increased cell utilization
06/10/1998EP0592688B1 Microprocessor system having dynamic RAM
06/10/1998DE19734908A1 Semiconductor memory with numerous pairs of bit lines
06/10/1998CN1184337A Semiconductor memory device and fabrication method thereof
06/10/1998CN1184336A Semi-conductor device
06/10/1998CN1184330A Semi-conductor memory device
06/10/1998CN1184317A Static semi-conductor memory device
06/10/1998CN1184316A Row redundancy block architecture
06/10/1998CN1184315A Static semiconductor memory device capable of reducing precharging power dissipation
06/09/1998US5765212 Memory control circuit that selectively performs address translation based on the value of a road start address
06/09/1998US5764966 Method and apparatus for reducing cumulative time delay in synchronizing transfer of buffered data between two mutually asynchronous buses
06/09/1998US5764653 Method and apparatus for detecting abnormal operation in a storage circuit by monitoring an associated reference circuit
06/09/1998US5764592 External write pulse control method and structure
06/09/1998US5764591 Memory device and memory control circuit
06/09/1998US5764590 Synchronous semiconductor memory device which allows switching of bit configuration
06/09/1998US5764588 Memory circuit
06/09/1998US5764587 Static wordline redundancy memory device
06/09/1998US5764585 Semiconductor memory device having main word lines and sub word lines
06/09/1998US5764584 Multi-bank synchronous semiconductor memory device
06/09/1998US5764582 Apparatus and method of refreshing a dynamic random access memory
06/09/1998US5764581 Dynamic ram with two-transistor cell
06/09/1998US5764576 Semiconductor memory device and method of checking same for defect
06/09/1998US5764573 Semiconductor device capable of externally and readily identifying set bonding optional function and method of identifying internal function of semiconductor device
06/09/1998US5764571 Electrically alterable non-volatile memory with N-bits per cell
06/09/1998US5764568 Method for performing analog over-program and under-program detection for a multistate memory cell
06/09/1998US5764567 Magnetic tunnel junction device with nonferromagnetic interface layer for improved magnetic field response
06/09/1998US5764566 Data holding circuit
06/09/1998US5764565 Static type semiconductor memory device with two word lines for one row
06/09/1998US5764564 Write-assisted memory cell and method of operating same