| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 05/19/1998 | US5754487 Bit line precharge circuit |
| 05/19/1998 | US5754486 Self-test circuit for memory integrated circuits |
| 05/19/1998 | US5754485 Dual port memory apparatus operating a low voltage to maintain low operating current during charging and discharging |
| 05/19/1998 | US5754481 Clock synchronous type DRAM with latch |
| 05/19/1998 | US5754478 Fast, low power, write scheme for memory circuits using pulsed off isolation device |
| 05/19/1998 | US5754477 Differential flash memory cell and method for programming |
| 05/19/1998 | US5754475 Bit line discharge method for reading a multiple bits-per-cell flash EEPROM |
| 05/19/1998 | US5754474 Variable threshold voltage adjustment circuit for semiconductor device |
| 05/19/1998 | US5754472 Flash memory device having a program path the same as a read pre-condition path |
| 05/19/1998 | US5754470 Apparatus for programming a voltage within a storage element |
| 05/19/1998 | US5754469 Page mode floating gate memory device storing multiple bits per cell |
| 05/19/1998 | US5754467 Semiconductor integrated circuit device and process for manufacturing the same |
| 05/19/1998 | US5754466 Ferroelectric memory having pair of reference cells |
| 05/19/1998 | US5754418 High voltage generation circuit for semiconductor memory device |
| 05/19/1998 | US5754075 Integrated circuits including power supply boosters and methods of operating same |
| 05/19/1998 | US5753950 Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming/erasing/reading method for the same |
| 05/19/1998 | US5753946 Ferroelectric memory |
| 05/19/1998 | US5753553 Method of fabricating ROMs by selectively forming sidewalls on wordlines |
| 05/14/1998 | WO1998020496A1 Spin dependent tunneling memory |
| 05/14/1998 | WO1998020495A1 Staggered row line firing in a single ras cycle |
| 05/14/1998 | WO1998020494A2 Memory circuit and method of operation therefor |
| 05/14/1998 | WO1998020401A1 Positive/negative high voltage charge pump system |
| 05/14/1998 | WO1998011689A3 Method of cryptological authentification in a scanning identification system |
| 05/14/1998 | DE19748675A1 Pre-read-out for memory component selecting lower memory field |
| 05/14/1998 | CA2269539A1 Spin dependent tunneling memory |
| 05/13/1998 | EP0840928A1 An integrated circuit having enable control circuitry |
| 05/13/1998 | CN1181632A Dynamic memory |
| 05/13/1998 | CN1181596A Semiconductor device with memory function and its data readout method |
| 05/13/1998 | CN1181505A Semiconductor device and internal function identification method of semiconductor device |
| 05/12/1998 | US5752270 Method of executing read and write operations in a synchronous random access memory |
| 05/12/1998 | US5751987 Distributed processing memory chip with embedded logic having both data memory and broadcast memory |
| 05/12/1998 | US5751656 Synchronous DRAM memory with asynchronous column decode |
| 05/12/1998 | US5751655 Synchronous type semiconductor memory device having internal operation timings determined by count values of an internal counter |
| 05/12/1998 | US5751653 DRAM with reduced leakage current |
| 05/12/1998 | US5751652 Semiconductor apparatus having a voltage unit and a backup unit for providing a reduced power consumption |
| 05/12/1998 | US5751651 Semiconductor integrated circuit device having a hierarchical power source configuration |
| 05/12/1998 | US5751650 Electric signal supply circuit and semiconductor memory device |
| 05/12/1998 | US5751648 Two stage sensing for large static memory arrays |
| 05/12/1998 | US5751645 Semiconductor memory device with reduced output noise |
| 05/12/1998 | US5751644 Data transition detect write control |
| 05/12/1998 | US5751643 Dynamic memory word line driver |
| 05/12/1998 | US5751642 Voltage control circuit for input and output lines of semiconductor memory device |
| 05/12/1998 | US5751640 Semiconductor memory device and method thereof |
| 05/12/1998 | US5751639 DRAM having a power supply voltage lowering circuit |
| 05/12/1998 | US5751635 Read circuits for analog memory cells |
| 05/12/1998 | US5751634 Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor |
| 05/12/1998 | US5751632 Device for and method of sensing data of multi-bit memory cell |
| 05/12/1998 | US5751628 Ferroelectric memory devices and method for testing them |
| 05/12/1998 | US5751627 Memory cell that can store data nonvolatily using a ferroelectric capacitor, and a semiconductor memory device including such a memory cell |
| 05/12/1998 | US5751626 Ferroelectric memory using ferroelectric reference cells |
| 05/12/1998 | US5751625 Ferroelectric memory and recording device using the same |
| 05/12/1998 | US5751170 Circuit for low voltage sense amplifier |
| 05/12/1998 | US5751044 Manufacture device of four transistor sram cell layout and device |
| 05/12/1998 | US5751012 Polysilicon pillar diode for use in a non-volatile memory cell |
| 05/12/1998 | US5750427 Non-volatile memory cell structure and process for forming same |
| 05/07/1998 | WO1998019309A1 Memory |
| 05/07/1998 | WO1998019307A1 High speed input buffer |
| 05/07/1998 | WO1998019241A1 Method and apparatus for correcting a multilevel cell memory by using error locating codes |
| 05/07/1998 | WO1998002886A3 Memory with fast decoding |
| 05/07/1998 | DE19748023A1 Line decoder for semiconductor memory, generating output signal |
| 05/07/1998 | DE19734719A1 Semiconductor memory e.g. high speed DRAM with data memory array |
| 05/07/1998 | DE19724717A1 Semiconductor memory and its readout process |
| 05/07/1998 | DE19721516A1 Microprocessor for real time emulation and testing |
| 05/06/1998 | EP0840448A2 A setup/hold time delay network |
| 05/06/1998 | EP0840328A2 Method and device for testing memory circuits |
| 05/06/1998 | EP0840326A2 Nonvolatile semiconductor memory device |
| 05/06/1998 | EP0840325A2 Improvements in or relating to memory devices |
| 05/06/1998 | EP0840324A2 Semiconductor memory and method for accessing the same |
| 05/06/1998 | EP0840323A2 Static semiconductor memory device with precharging circuits having similar configuration of memory cells |
| 05/06/1998 | EP0839375A2 Pipelined address memories, and systems and methods using the same |
| 05/06/1998 | EP0551419B1 Integrated circuit systems and method for analog signal recording and playback |
| 05/06/1998 | CN1180960A Counter and semiconductor memory including counter |
| 05/06/1998 | CN1180930A Decision method for semiconductor integrated circuit whether or not qualified and semiconductor integrated circuit |
| 05/06/1998 | CN1180900A Two port memory for simultaneously inputting and outputting data |
| 05/05/1998 | US5749086 Simplified clocked DRAM with a fast command input |
| 05/05/1998 | US5748914 Protocol for communication with dynamic memory |
| 05/05/1998 | US5748849 Neural processor comprising distributed synaptic cells |
| 05/05/1998 | US5748641 Test circuit of semiconductor memory device having data scramble function |
| 05/05/1998 | US5748561 Semiconductor memory device with fast successive read operation |
| 05/05/1998 | US5748560 Synchronous semiconductor memory device with auto precharge operation easily controlled |
| 05/05/1998 | US5748558 Semiconductor memory device |
| 05/05/1998 | US5748557 Address buffer for high-speed address inputting |
| 05/05/1998 | US5748556 Tristatable driver for internal data bus lines |
| 05/05/1998 | US5748554 Memory and method for sensing sub-groups of memory elements |
| 05/05/1998 | US5748553 Semiconductor memory device having extended margin in latching input signal |
| 05/05/1998 | US5748552 DRAM implementation for more efficient use of silicon area |
| 05/05/1998 | US5748547 High performance semiconductor memory devices having multiple dimension bit lines |
| 05/05/1998 | US5748546 Sensing scheme for flash memory with multilevel cells |
| 05/05/1998 | US5748544 Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory |
| 05/05/1998 | US5748541 Latch circuit operating in synchronization with clock signals |
| 05/05/1998 | US5748540 Prevention of erroneous operation in equalizing operation in semiconductor memory device |
| 05/05/1998 | US5748538 OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array |
| 05/05/1998 | US5748534 Feedback loop for reading threshold voltage |
| 05/05/1998 | US5748533 Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell |
| 05/05/1998 | US5748530 Non-voltile memory device, non-volatile memory cell and method of adjusting the threshold value of the non-volatile memory cell and each of plural transistors |
| 05/05/1998 | US5748524 MRAM with pinned ends |
| 05/05/1998 | US5748523 Integrated circuit magnetic memory element having a magnetizable member and at least two conductive winding |
| 05/05/1998 | US5748520 Semiconductor memory device having minimal leakage current |
| 05/05/1998 | US5748519 Method of selecting a memory cell in a magnetic random access memory device |
| 05/05/1998 | US5748201 Semiconductor memory device having multiple modes that allow the cell array to be divided into a variable number of portions |