Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2007
05/17/2007US20070109867 Use of Data Latches in Cache Operations of Non-Volatile Memories
05/17/2007US20070109866 Method of programming and verifying cells of a nonvolatile memory and relative nand flash memory
05/17/2007US20070109865 Radiation tolerant combinational logic cell
05/17/2007US20070109864 Selective Operation of a Multi-State Non-Volatile Memory System in a Binary Mode
05/17/2007US20070109862 Flash memory device and word line enable method thereof
05/17/2007US20070109859 Latched Programming of Memory and Method
05/17/2007US20070109858 Novel Method and Structure for Efficient Data Verification Operation for Non-Volatile Memories
05/17/2007US20070109851 Method of manufacturing non-volatile memory and method of operating non-volatile memory array
05/17/2007US20070109847 Non-Volatile Memory and Method With Improved Sensing
05/17/2007US20070109844 Semiconductor memory device and method for driving semiconductor memory device
05/17/2007US20070109843 Phase Change Memory Device and Manufacturing Method
05/17/2007US20070109842 Magnetic memory layers thermal pulse transitions
05/17/2007US20070109841 Load-balanced apparatus of memory
05/17/2007US20070109840 Memory write circuit
05/17/2007US20070109839 MRAM read sequence using canted bit magnetization
05/17/2007US20070109838 Magnetic memory device
05/17/2007US20070109837 System comprising an electronic device and method of operating a system
05/17/2007US20070109836 Thermally insulated phase change memory device and manufacturing method
05/17/2007US20070109835 Cross-point RRAM memory array having low bit line crosstalk
05/17/2007US20070109834 Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same
05/17/2007US20070109699 Semiconductor integrated circuit
05/17/2007US20070109360 Nozzle arrangement with an ink ejecting displaceable roof structure
05/17/2007US20070109034 Semiconductor device
05/17/2007US20070109030 Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics
05/17/2007US20070108482 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
05/16/2007EP1784836A1 Apparatus and method for improving dynamic refresh in a semiconductor memory device by temperature measurement
05/16/2007CN1965418A Layered resistance variable memory device and method of fabrication
05/16/2007CN1965404A Semiconductor storage
05/16/2007CN1965371A Erase method for multi-level bit flash memory
05/16/2007CN1964194A N-shape dominoes register with accelerate non-charge path
05/16/2007CN1963949A Non-volatile phase-change memory device and method of reading the same
05/16/2007CN1963946A Non-volatile memory devices with transistor and diode as on-off cell
05/16/2007CN1963945A Semiconductor memory device and method for driving semiconductor memory device
05/16/2007CN1963797A Systems and methods for automatically eliminating imbalance between signals
05/16/2007CN1316744C Antifuse reroute of dies
05/16/2007CN1316598C Integrated circuit and method for programming charge storage memory cells
05/16/2007CN1316503C Integrated memory and method for production and operation of integrated memory
05/16/2007CN1316381C Self-refresh apparatus and method
05/15/2007WO2007029223A1 Method for increasing storage capacity of a memory device
05/15/2007US7219272 Semiconductor integrated circuit with memory redundancy circuit
05/15/2007US7219205 Memory controller device
05/15/2007US7219200 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions
05/15/2007US7218569 Memory circuit, and method for reading out data contained in the memory circuit using shared command signals
05/15/2007US7218565 Method and apparatus for independently refreshing memory capacitors
05/15/2007US7218556 Method of writing to MRAM devices
05/15/2007US7218555 Imaging cell that has a long integration period and method of operating the imaging cell
05/15/2007US7218553 Method for programming memory cells including transconductance degradation detection
05/15/2007US7218552 Last-first mode and method for programming of non-volatile memory with reduced program disturb
05/15/2007US7218551 Multiple level cell memory device with single bit per cell, re-mappable memory block
05/15/2007US7218550 Magnetic storage device
05/15/2007US7218549 Memory cell with stability switch for stable read operation and improved write operation
05/15/2007US7218548 Semiconductor memory device for low voltage
05/15/2007US7218547 ROM embedded DRAM with anti-fuse programming
05/15/2007US7218546 Integrated circuit device provided with series-connected TC parallel unit ferroelectric memory and method for testing the same
05/15/2007US7218545 Polymer de-imprint circuit using negative voltage
05/15/2007US7218159 Flip-flop circuit having majority-logic circuit
05/15/2007US7218142 Switch matrix circuit, logical operation circuit, and switch circuit
05/15/2007US7217963 Semiconductor integrated circuit device
05/15/2007US7217577 Structure/method to fabricate a high-performance magnetic tunneling junction MRAM
05/15/2007US7217048 Pagewidth printer and computer keyboard combination
05/15/2007US7216957 Micro-electromechanical ink ejection mechanism that incorporates lever actuation
05/15/2007CA2520140C Split-channel antifuse array architecture
05/10/2007WO2007053517A2 Enhanced toggle-mram memory device
05/10/2007WO2007053340A2 Magnetic tunnel junction current sensors
05/10/2007WO2007052426A1 Semiconductor memory device having cross-point structure
05/10/2007WO2007052207A1 Memory matrix composed of memory cells each constituted by a transistor and a memory element connected in parallel
05/10/2007WO2007052039A1 Non-volatile memory device
05/10/2007WO2007051795A1 Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same
05/10/2007WO2007051285A1 Dynamic random access memory device and method for self-refreshing memory cells
05/10/2007WO2006029098A3 System and method for proactive drive replacement in high availability storage systems
05/10/2007US20070104018 Apparatus and method for improving dynamic refresh in a memory device
05/10/2007US20070104004 Multi-Bit-Per-Cell Flash EEprom Memory with Refresh
05/10/2007US20070103994 Regulation circuit for inductive charge pump
05/10/2007US20070103991 Integrated code and data flash memory
05/10/2007US20070103988 Circuit arrangement and method for controlling an inductive load
05/10/2007US20070103987 Read operation for non-volatile storage that includes compensation for coupling
05/10/2007US20070103976 Flexible and Area Efficient Column Redundancy for Non-Volatile Memories
05/10/2007US20070103973 Memory architecture
05/10/2007US20070103972 Non-volatile phase-change memory device and method of reading the same
05/10/2007US20070103971 Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device
05/10/2007US20070103970 Non-volatile ferromagnegtic memory having sensor circuitry shared with its state change circuitry
05/10/2007US20070103969 Method and apparatus for reading data from a ferromagnetic memory cell
05/10/2007US20070103968 Non-volatile memory device conducting comparison operation
05/10/2007US20070103967 Non-homogeneous shielding of an mram chip with magnetic field sensor
05/10/2007US20070103966 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
05/10/2007US20070103965 Memory cell with a vertically integrated delay element
05/10/2007US20070103964 Resistive memory devices including selected reference memory cells and methods of operating the same
05/10/2007US20070103963 Non-volatile memory devices and method thereof
05/10/2007US20070103962 Programmable memory cell and operation method
05/10/2007US20070103961 RAM cell with soft error protection using ferroelectric material
05/10/2007US20070103960 Method for operating a data storage apparatus employing passive matrix addressing
05/10/2007US20070102691 Silver-selenide/chalcogenide glass stack for resistance variable memory
05/10/2007DE10239515B4 Halbleiterspeicher-Steuerverfahren und Halbleiterspeichervorrichtung A semiconductor memory control method and the semiconductor memory device
05/10/2007DE102006047943A1 Arbeitszykluskorrekturvorrichtung Duty cycle corrector
05/10/2007DE102006045724A1 Direktzugriffsspeicher mit einer ersten und einer zweiten Spannungsquelle Random access memory having a first and a second voltage source
05/10/2007DE102005053496A1 Memory unit e.g. programmable read only memory unit, has bit line, ground line and memory cells, which are assigned to transistors, where bit line and ground line run parallel to each other
05/10/2007DE102005052906A1 Sensoranordnung Sensor array
05/10/2007DE102005045311B4 Halbleiterspeicher, insbesondere Halbleiterspeicher mit Leseverstärker und Bitleitungs-Schalter A semiconductor memory, in particular semiconductor memory having sense amplifiers and bit line switch
05/10/2007DE102004051958B4 Schaltungsanordnung und Verfahren zum Einstellen von Betriebsparametern in einem RAM-Baustein Circuit arrangement and method for setting operating parameters in a RAM module
05/10/2007DE10156749B4 Speicher, Prozessorsystem und Verfahren zum Durchführen von Schreiboperationen auf einen Speicherbereich Memory, processor system and method for performing write operations to a storage area
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