Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
01/2009
01/27/2009US7483295 MTJ sensor including domain stable free layer
01/27/2009US7483294 Read, write, and erase circuit for programmable memory devices
01/27/2009US7483293 Method for improving the thermal characteristics of semiconductor memory cells
01/27/2009US7483292 Memory cell with separate read and program paths
01/27/2009US7483291 Magneto-resistance effect element, magnetic memory and magnetic head
01/27/2009US7483290 Nonvolatile memory utilizing hot-carrier effect with data reversal function
01/27/2009US7483289 Synchronous SRAM capable of faster read-modify-write operation
01/27/2009US7483288 Memory device
01/27/2009US7483287 Semiconductor memory
01/27/2009US7483285 Memory devices using carbon nanotube (CNT) technologies
01/27/2009US7483245 Magnetoresistance effect element, and magnetic head and magnetic recording and/or reproducing system utilizing the magnetoresistance element
01/27/2009US7483050 Camera and controlling processing system
01/27/2009US7483033 Storage device
01/27/2009US7482650 Method of manufacturing a semiconductor integrated circuit device having a columnar laminate
01/27/2009US7482648 Electronic device and method of manufacturing the same
01/27/2009US7482644 Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory
01/27/2009US7482624 Organic electronic circuit and method for making the same
01/27/2009US7481518 Ink jet printhead integrated circuit with surface-processed thermal actuators
01/22/2009WO2009011484A1 Magnetic memory cell
01/22/2009WO2009011052A1 Memory refresh device and memory refresh method
01/22/2009WO2009010595A1 Magnetoelectric device and method for writing non-volatile information on said device
01/22/2009WO2007062378A3 Array source line (avss) controlled high voltage regulation for programming flash or ee array
01/22/2009WO2006072223A4 Memory device for recording and storage of information in at least ternary code
01/22/2009US20090024884 Memory controller method and system compensating for memory cell data losses
01/22/2009US20090022001 Semiconductor memory device
01/22/2009US20090021993 Semiconductor memory device
01/22/2009US20090021987 Analog sensing of memory cells in a solid state memory device
01/22/2009US20090021986 Operating method of non-volatile memory device
01/22/2009US20090021984 Methods and structures for highly efficient hot carrier injection programming for non-volatile memories
01/22/2009US20090021981 Nonvolatile memory device including circuit formed of thin film transistors
01/22/2009US20090021979 Gate stack, capacitorless dynamic random access memory including the gate stack and methods of manufacturing and operating the same
01/22/2009US20090021977 Phase change material containing carbon, memory device including the phase change material, and method of operating the memory device
01/22/2009US20090021976 Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module
01/22/2009US20090021975 Method and media for improving ferroelectric domain stability in an information storage device
01/22/2009US20090021972 Memory array using mechanical switch and method for operating thereof
01/22/2009DE10332186B4 Integrierte Halbleiterspeicherschaltung und zugehöriges Betriebsverfahren Integrated semiconductor memory circuit and associated operating method
01/22/2009DE10316128B4 Synchroner Halbleiterbaustein und Verfahren zum Einstellen einer Datenausgabezeit A synchronous semiconductor device and method for setting a data output time
01/22/2009DE10202903B4 Magnetoresistive Speicherzelle mit polaritätsabhängigem Widerstand und Speicherzelle Magnetoresistive memory cell with polaritätsabhängigem resistance and memory cell
01/22/2009DE102008033691A1 Verfahren und Vorrichtung für einen frühzeitigen Schreibvorgang Method and apparatus for early writing
01/22/2009DE10153658B4 Magnetoresistive Speicherzelle mit Anordnung zur Minimierung der Néel-Wechselwirkung zwischen zwei ferromagnetischen Schichten beiderseits einer nichtferromagnetischen Trennschicht und Verfahren zu Herstellung der magnetoresistiven Speicherzelle Magnetoresistive memory cell array to minimize the Néel interaction between the two ferromagnetic layers on either side of a non-ferromagnetic separating layer and process for producing the magnetoresistive memory cell
01/22/2009DE10134495B4 Speicherbauelement und Verarbeitungsverfahren für Objekt-Tiefendaten Memory device and method for processing object-depth data
01/21/2009EP2016590A2 Non-volatile memory with background data latch caching during read operations and methods therefor
01/21/2009EP2016588A1 Dynamic random access memory with fully independent partial array refresh function
01/21/2009EP1490877B1 Synthetic-ferrimagnet sense-layer for high density mram applications
01/21/2009CN101351847A Alternate sensing techniques for non-volatile memory
01/21/2009CN101350360A Three-dimensional stacking non-phase-change caused resistance conversion storage apparatus and manufacturing method thereof
01/21/2009CN101350225A Nonvolatile memory device using variable resistive materials
01/21/2009CN101350216A Reduced signal level support for memory devices
01/21/2009CN100454599C Spin-injection field effect transistor, magnetic ram, and reconfigurable logical circuit
01/21/2009CN100454576C Semiconductor component and its manufacturing method and memory element and its operating method
01/21/2009CN100454440C Combined static RAM and mask ROM storage unit
01/21/2009CN100454439C Non-volatile semiconductor memory device
01/21/2009CN100454438C DDR memory controller and matrix line access method for matrix transposition
01/21/2009CN100454437C Semiconductor memory device and data read and write method thereof
01/21/2009CN100454436C Semiconductor memory device
01/21/2009CN100454435C Output driving strength correcting circuit and method for DRAM
01/21/2009CN100454434C Multi-port memory cells
01/21/2009CN100454433C Write line design in MRAM and its manufacturing method
01/21/2009CN100454432C Relayed electric pulse used in magnetic resistor
01/20/2009US7480776 Circuits and methods for providing variable data I/O width for semiconductor memory devices
01/20/2009US7480774 Method for performing a command cancel function in a DRAM
01/20/2009US7480762 Erase block data splitting
01/20/2009US7480760 Rotational use of memory to minimize write cycles
01/20/2009US7480200 Semiconductor memory device suitable for mounting on portable terminal
01/20/2009US7480199 Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal refresh rate
01/20/2009US7480197 Implementing calibration of DQS sampling during synchronous DRAM reads
01/20/2009US7480194 Data input/output (I/O) apparatus for use in a memory device
01/20/2009US7480192 Pull-up voltage circuit
01/20/2009US7480187 Nonvolatile semiconductor memory with low-loading bit line architecture and method of programming the same
01/20/2009US7480186 NROM flash memory with self-aligned structural charge separation
01/20/2009US7480185 Ballistic injection NROM flash memory
01/20/2009US7480184 Maximum likelihood statistical method of operations for multi-bit semiconductor memory
01/20/2009US7480183 Semiconductor memory device, and read method and read circuit for the same
01/20/2009US7480181 Non-volatile memory with background data latch caching during read operations
01/20/2009US7480180 Semiconductor memory device comprising plural source lines
01/20/2009US7480179 System that compensates for coupling during programming
01/20/2009US7480177 Page buffer and multi-state nonvolatile memory device including the same
01/20/2009US7480176 Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory
01/20/2009US7480175 Magnetic tunnel junction device and writing/reading for said device
01/20/2009US7480174 Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated
01/20/2009US7480173 Spin transfer MRAM device with novel magnetic free layer
01/20/2009US7480172 Programming scheme for segmented word line MRAM array
01/20/2009US7480171 MRAM based on vertical current writing and its control method
01/20/2009US7480170 Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)
01/20/2009US7480169 Ideal CMOS SRAM system implementation
01/20/2009US7480168 Semiconductor memory device
01/20/2009US7480167 Set programming methods and write driver circuits for a phase-change memory array
01/20/2009US7479677 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
01/20/2009US7479212 Method of manufacturing high-density data storage medium
01/15/2009WO2009009564A1 Memory cells with power switch circuit for improved low voltage operation
01/15/2009WO2009008081A1 Semiconductor device
01/15/2009WO2009008079A1 Semiconductor memory device and system
01/15/2009US20090019218 Non-Volatile Memory And Method With Non-Sequential Update Block Management
01/15/2009US20090019217 Non-Volatile Memory And Method With Memory Planes Alignment
01/15/2009US20090019215 Method and device for performing cache reading
01/15/2009US20090016142 Semiconductor memory device, and method of controlling the same
01/15/2009US20090016116 Method of Programming and Erasing a Non-Volatile Memory Array
01/15/2009US20090016105 Nonvolatile memory utilizing mis memory transistors capable of multiple store operations
01/15/2009US20090016102 Nonvolatile semiconductor memory device which stores multi-value information
01/15/2009US20090016101 Reading Technique for Memory Cell With Electrically Floating Body Transistor