| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 06/16/2011 | US20110145477 Flash translation layer using phase change memory |
| 06/16/2011 | US20110145476 Persistent Content in Nonvolatile Memory |
| 06/16/2011 | US20110141832 Program cycle skip |
| 06/16/2011 | US20110141816 Tracking Cells For A Memory System |
| 06/16/2011 | US20110141813 Use of emerging non-volatile memory elements with flash memory |
| 06/16/2011 | US20110141807 Semiconductor device and control method therefor |
| 06/16/2011 | US20110141804 Method and system for providing dual magnetic tunneling junctions usable in spin transfer torque magnetic memories |
| 06/16/2011 | US20110141803 Magnetic tunnel junction devices, electronic devices including a magnetic tunneling junction device and methods of fabricating the same |
| 06/16/2011 | US20110141802 Method and system for providing a high density memory cell for spin transfer torque random access memory |
| 06/16/2011 | US20110141801 Use of symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory |
| 06/16/2011 | US20110141800 Phase-change memory device |
| 06/16/2011 | US20110141799 Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming |
| 06/16/2011 | US20110141798 Amorphous Semiconductor Threshold Switch Volatile Memory Cell |
| 06/16/2011 | US20110141797 Creating spin-transfer torque in oscillators and memories |
| 06/16/2011 | US20110141796 Magnetic Tunnel Junction Device and Fabrication |
| 06/16/2011 | US20110141795 Multi-port memory based on dram core |
| 06/16/2011 | US20110141794 Semiconductor memory device and inspecting method of the same |
| 06/16/2011 | US20110141793 Semiconductor memory device |
| 06/16/2011 | US20110141792 Read/write structures for a three dimensional memory |
| 06/16/2011 | US20110141788 Page register outside array and sense amplifier interface |
| 06/16/2011 | US20110140741 Integrating receiver with precharge circuitry |
| 06/16/2011 | DE10343525B4 Verfahren zum Betreiben von Halbleiterbausteinen, Steuervorrichtung für Halbleiterbausteine und Anordnung zum Betreiben von Speicherbausteinen A method of operating of semiconductor devices, the control device for semiconductor devices and arrangement for operating the memory blocks |
| 06/16/2011 | DE10233878B4 Integrierter synchroner Speicher sowie Speicheranordnung mit einem Speichermodul mit wenigstens einem synchronen Speicher Integrated synchronous memory and memory device having a memory module having at least one synchronous memory |
| 06/16/2011 | DE10212631B4 Speicherungssysteme mit atomarer Auflösung mit verbessertem Magnetfeldschutz Storage systems at atomic resolution with improved protection against magnetic fields |
| 06/16/2011 | DE10031575B4 Halbleiterspeicherbauelement The semiconductor memory device |
| 06/16/2011 | DE10009346B4 Integrierte Schreib-/Leseschaltung zur Auswertung von zumindest einer Bitline in einem DRAM Speicher Integrated read / write circuit for evaluating at least one bitline in a DRAM memory |
| 06/15/2011 | EP2333826A1 Magnetic memory element and storage device using same |
| 06/15/2011 | EP2333781A1 Maintenance operations for multi-level data storage cells |
| 06/15/2011 | EP2333780A1 Maintenance operations for multi-level data storage cells |
| 06/15/2011 | EP2333779A1 Method of controlling a SeOI dram memory cell having a second control gate buried under the insulating layer |
| 06/15/2011 | EP2332147A2 Multi-pass programming for memory with reduced data storage requirement |
| 06/15/2011 | EP2332146A1 Data state-based temperature compensation during sensing in non-volatile memory |
| 06/15/2011 | EP2332145A1 Symmetric stt-mram bit cell design |
| 06/15/2011 | EP2332144A1 Stt-mram bit cell having a rectangular bottom electrode plate |
| 06/15/2011 | EP2332142A1 Memory device for resistance-based memory applications |
| 06/15/2011 | EP2332049A1 Cross-point magnetoresistive memory |
| 06/15/2011 | EP1673780B1 Ac sensing for a resistive memory |
| 06/15/2011 | EP1668646B1 Method and apparatus for implicit dram precharge |
| 06/15/2011 | EP1497733B1 Destructive-read random access memory system buffered with destructive-read memory cache |
| 06/15/2011 | CN1826658B Compensating a long read time of a memory device in data comparison and write operations |
| 06/15/2011 | CN1822219B Magnetoresistance device including layered ferromagnetic structure, and method of manufacturing the same |
| 06/15/2011 | CN1790544B 半导体存储器装置 The semiconductor memory device |
| 06/15/2011 | CN1783337B Magnetic random access memory |
| 06/15/2011 | CN1679111B Device writing to a plurality of rows in a memory matrix simultaneously |
| 06/15/2011 | CN1679109B Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device |
| 06/15/2011 | CN1622221B Apparatus and method of analyzing magnetic random access memory |
| 06/15/2011 | CN1610001B Semiconductor memory device with magnetoresistance elements and method of writing data into the same |
| 06/15/2011 | CN102099865A Methods and apparatus for programming multiple program values per signal level in flash memories |
| 06/15/2011 | CN102099864A Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same |
| 06/15/2011 | CN102099862A Gate level reconfigurable magnetic logic |
| 06/15/2011 | CN102097374A Phase change random access memory and manufacturing method thereof |
| 06/15/2011 | CN102097125A PCM (pulse code modulation) write operation method |
| 06/15/2011 | CN102097124A Semiconductor devices having on-die termination structures and termination methods performed in the semiconductor devices |
| 06/15/2011 | CN102097123A Anti-single event effect static random access memory unit |
| 06/15/2011 | CN102097122A NAND flash controller circuit of multi-channel shared data cache region |
| 06/15/2011 | CN102097121A Internal negative voltage generation device |
| 06/15/2011 | CN102096640A NAND Flash load balance algorithm of low resource occupancy rate |
| 06/15/2011 | CN101567214B Line selector applicable to reading and wiring functions of nine-transistor memory unit |
| 06/15/2011 | CN101271727B Magnetic memory cell writing method and magnetic memory array structure |
| 06/15/2011 | CN101261880B Programmable conductor random access memory and method for sensing same |
| 06/15/2011 | CN101241756B Memory cell with separate read and program paths |
| 06/14/2011 | US7962767 Integrated circuit having obscured state change circuitry |
| 06/14/2011 | US7961545 Semiconductor device |
| 06/14/2011 | US7961540 Dynamic data restore in thyristor-based memory device |
| 06/14/2011 | US7961534 Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof |
| 06/14/2011 | US7961524 Method for driving a nonvolatile semiconductor memory device |
| 06/14/2011 | US7961523 Nonvolatile memory device and programming method |
| 06/14/2011 | US7961522 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells |
| 06/14/2011 | US7961521 Sensing circuit for flash memory device operating at low power supply voltage |
| 06/14/2011 | US7961517 Program and read trim setting |
| 06/14/2011 | US7961516 NAND flash memory and memory system |
| 06/14/2011 | US7961512 Adaptive algorithm in cache operation with dynamic data latch requirements |
| 06/14/2011 | US7961510 Integrated circuits to control access to multiple layers of memory in a solid state drive |
| 06/14/2011 | US7961509 Spin-transfer torque memory self-reference read and write assist methods |
| 06/14/2011 | US7961508 Phase-change random access memory |
| 06/14/2011 | US7961507 Non-volatile memory with resistive access component |
| 06/14/2011 | US7961506 Multiple memory cells with rectifying device |
| 06/14/2011 | US7961505 Electronic device, method of manufacturing the same, and storage device |
| 06/14/2011 | US7961504 Phase change random access memory device and related methods of operation |
| 06/14/2011 | US7961503 Magnetic floating gate memory |
| 06/14/2011 | US7961501 Radiation sensors and single-event-effects suppression devices |
| 06/14/2011 | US7961500 Semiconductor device |
| 06/14/2011 | US7961499 Low leakage high performance static random access memory cell using dual-technology transistors |
| 06/14/2011 | US7961498 Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells |
| 06/14/2011 | US7961497 Variable resistive memory punchthrough access method |
| 06/14/2011 | US7961496 Resistive memory cells and devices having asymmetrical contacts |
| 06/14/2011 | US7961495 Programmable resistance memory with feedback control |
| 06/14/2011 | US7961494 Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same |
| 06/14/2011 | US7961493 Programmable device |
| 06/14/2011 | US7961492 Charge storage circuit, voltage stabilizer circuit, method for storing charge using the same |
| 06/14/2011 | US7961488 Method for modifying data more than once in a multi-level cell memory location within a memory array |
| 06/14/2011 | US7961249 Digital camera having interconnected image processing units |
| 06/14/2011 | US7959263 Printhead integrated circuit with a solenoid piston |
| 06/09/2011 | WO2011068694A2 Dram sense amplifier that supports low memory-cell capacitance |
| 06/09/2011 | WO2011066650A1 Method and system for a run-time reconfigurable computer architecture |
| 06/09/2011 | US20110138251 Memory system and method using partial ecc to achieve low power refresh and fast access to data |
| 06/09/2011 | US20110134714 Semiconductor memory device changing refresh interval depending on temperature |
| 06/09/2011 | US20110134696 Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks |
| 06/09/2011 | US20110134691 Scalable multi-function and multi-level nano-crystal non-volatile memory device |
| 06/09/2011 | US20110134690 METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER |