Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
07/1990
07/03/1990US4939735 Information handling system having serial channel to control unit link
07/03/1990US4939644 Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system
07/03/1990US4939643 Fault tolerant digital data processor with improved bus protocol
07/03/1990US4939507 Virtual and emulated objects for use in the user interface of a display screen of a display processor
06/1990
06/29/1990CA2003418A1 Computer message & screen communications in a multi-lingual network
06/28/1990WO1990007156A1 Bus interface controller for computer graphics
06/28/1990WO1990007151A1 Data management system
06/28/1990DE3843725A1 Circuit arrangement to control the input of data units into a memory
06/28/1990CA2006686A1 Ordering system using distributed graphics and centralized text
06/27/1990EP0375664A2 Local area network for digital data processing system
06/27/1990EP0375143A2 Shared object status indicating
06/27/1990EP0375139A2 Classified document transmission control
06/27/1990EP0375138A2 Restricting electronic message traffic
06/27/1990EP0375121A2 Method and apparatus for efficient DRAM control
06/27/1990EP0375105A2 Memory apparatus for multiple processor systems
06/27/1990EP0374764A2 Data transfer apparatus
06/27/1990EP0374521A2 Least recently used arbiter with programmable high priority mode and performance monitor
06/27/1990EP0374432A2 Channel diagnostic apparatus and method
06/27/1990EP0374338A1 Shared intelligent memory for the interconnection of distributed micro processors
06/27/1990EP0374337A1 Load balancing technique in shared memory with distributed structure
06/26/1990US4937815 Transmission control system for regulating
06/26/1990US4937783 Peripheral controller for executing multiple event-count instructions and nonevent-count instructions in a prescribed parallel sequence
06/26/1990US4937781 Dual port ram with arbitration status register
06/26/1990US4937737 Process transparent multi storage mode data transfer and buffer control
06/26/1990US4937734 High speed bus with virtual memory data transfer and rerun cycle capability
06/26/1990US4937567 Communication adapter for store loop communication system
06/26/1990US4937036 Concurrent display of data from two different display processors and user interface therefore
06/26/1990US4936785 Interchangeable adapter module for electronic devices
06/20/1990EP0374134A2 Local area network for digital data processing system
06/20/1990EP0374133A2 Local area network for digital data processing system
06/20/1990EP0374132A2 Local area network for digital data processing system
06/20/1990EP0374131A2 Local area network for digital data processing system
06/20/1990EP0374074A2 Computer system having efficient data transfer operations
06/20/1990EP0373773A1 Disengaging electrical circuit boards from power-supply units
06/20/1990EP0373393A1 Information processing system
06/20/1990EP0373299A2 Method and apparatus for memory routing scheme
06/20/1990CN1043211A Electronic system having a plurality of removable units
06/20/1990CN1008484B Processor i/o and interrupt filters
06/20/1990CN1008483B Data transmission device
06/19/1990US4935894 Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information
06/19/1990US4935868 Multiple port bus interface controller with slave bus
06/19/1990US4935866 Multiprocessor control system
06/19/1990US4935719 Comparator circuitry
06/19/1990CA2003554A1 Bus interface controller for computer graphics
06/19/1990CA1270576A1 Ic device compatible with input signals in the formats for two-line and four-line type bus lines
06/19/1990CA1270575A1 I/o handler
06/13/1990EP0373130A2 Method for maintaining the integrity of ties in a layered communications system
06/13/1990EP0373043A1 Electronic system with several removable units
06/13/1990EP0372534A2 Data transmission system
06/13/1990EP0372021A1 Universal connector device
06/13/1990CN1043023A Microprocessor vectored interrupts
06/12/1990US4933935 Communications systems
06/12/1990US4933846 Network communications adapter with dual interleaved memory banks servicing multiple processors
06/12/1990US4933845 Reconfigurable bus
06/12/1990US4933840 I/O control system using buffer full/empty and zero words signals to control DMA read/write commands
06/12/1990CA1270338A1 Data processing system for processing units having different throughputs
06/12/1990CA1270336A1 Higher order language-directed computer
06/07/1990DE3932863A1 Verfahren und anordnung zur busvergabe an datenverarbeitende einrichtungen Method and arrangement for bus arbitration of data processing equipment
06/06/1990EP0371772A2 Memory accessing switch network
06/06/1990EP0371610A2 Deferred request status confirmation
06/06/1990EP0371609A2 Electronic mail systems
06/06/1990EP0371607A2 Electronic mail systems
06/06/1990EP0371605A2 Electronic mail systems
06/06/1990EP0371603A2 Methods of managing stapled documents
06/06/1990EP0371377A2 A distributed terminal driver protocol
06/06/1990EP0371296A2 Microcomputer interface arrangement
06/06/1990EP0371166A1 Disk storage device simulating memory module
06/06/1990EP0371034A1 Method and apparatus for data buffer management
06/06/1990EP0258350B1 Method for data exchange between a first and a second processor
06/06/1990CN2058034U Processor with improved electromagnetic radiation control function
06/05/1990US4932040 Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems
06/05/1990US4932021 Path learning feature for an automated telemarketing system
06/05/1990US4931983 Data processor capable of accessing the content of internal counters at a high speed
06/05/1990US4931925 High speed byte data rearranging processor
06/05/1990US4931923 Computer system for automatically reconfigurating memory space to avoid overlaps of memory reserved for expansion slots
06/05/1990US4931922 Method and apparatus for monitoring peripheral device communications
06/05/1990CA1270065A1 Data distribution apparatus and method
06/05/1990CA1270064A2 Digital computer with interleaved memory elements
06/01/1990CA2004254A1 Distributed terminal driver protocol
05/1990
05/31/1990DE3939626A1 Electronic mail system - has terminal with memory having main text area that cannot be manipulated
05/30/1990EP0370929A2 Kernel testing interface and method for automating diagnostics of microprocessor-based systems
05/30/1990EP0370628A2 Pipeline computer system having order preservation
05/30/1990EP0370274A2 Personal computer/host emulation system for handling host data with personal computer application programs at personal computers
05/30/1990EP0370223A2 Decentralised control unit, particularly for a rotary printing press, linked by a bus to a plurality of peripheral units
05/30/1990EP0370189A2 Modular computer system
05/29/1990US4930159 Method of disposal
05/29/1990US4930103 Data transmission method in a digital transmission network and apparatus for implimenting same
05/29/1990US4930070 Interrupt control method for multiprocessor system
05/29/1990US4930069 Mechanism and method for transferring data between bus units having varying master and slave DMA capabilities
05/29/1990US4930068 Data processor having different interrupt processing modes
05/29/1990US4930066 Multiport memory system
05/29/1990US4930065 Automatic data channels for a computer system
05/29/1990CA1269771A1 Method for bus access for data transmission through a multiprocessor bus
05/29/1990CA1269770A1 Communications systems
05/29/1990CA1269734A1 Fault tolerant dual port serial link controller
05/23/1990EP0369964A2 Multiple data format interface
05/23/1990EP0369773A2 Queue buffer memory control system
05/23/1990EP0369405A2 Bus driver integrated circuit and a clocked inverter for use therein
05/23/1990EP0369365A2 Monolithic skew reduction scheme for separately clocked data transfers
05/23/1990EP0369264A2 Multiprocessor system having distributed shared resources and deadlock prevention
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