Patents
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
07/1991
07/09/1991US5031095 Data transmission apparatus
07/09/1991US5031094 Switch controller
07/09/1991US5031091 Channel control system having device control block and corresponding device control word with channel command part and I/O command part
07/09/1991US5030857 High speed digital computer data transfer system having reduced bus state transition time
07/09/1991CA2031743A1 Electronic keying of multi-board systems
07/06/1991WO1991010183A1 System for interconnecting router elements with parallel computer
07/06/1991CA2047207A1 Network and method for interconnecting router elements within parallel computer system
07/03/1991EP0435806A2 Fault-tolerant serial attachment of remote high-speed I/O busses
07/03/1991EP0435613A2 Bus interface controller with bus isolation capability for redundant system implementations
07/03/1991EP0435092A2 Data processing system with direct memory access controller and method for varying communication bus masterchip in response to prioritized interrupt requests.
07/03/1991EP0435046A2 Procedure for reestablishing the original cell sequence, in particular in an ATM switch, as well as output module for that switch
07/03/1991CN1013069B Multi-link chip
07/03/1991CN1013068B Computer system having programmable dma control
07/02/1991US5029284 Precision switchable bus terminator circuit
07/02/1991US5029124 Method and apparatus for providing high speed parallel transfer of bursts of data
07/02/1991US5029104 Prestaging objects in a distributed environment
07/02/1991US5029076 Apparatus and method for providing a settling time cycle for a system bus in a data processing system
07/02/1991US5029074 Bus adapter unit for digital processing system
07/02/1991US5029073 Method for fast establishing a co-processor to memory linkage by main processor
07/02/1991CA1285659C Local area network with biasing arrangement for facilitating accesscontention between work stations connected to a common bus
07/02/1991CA1285658C Cpu channel to cpu channel extender
06/1991
06/29/1991CA2032423A1 Bus interface controller with bus isolation capability for redundant system implementations
06/27/1991WO1991010191A1 Object oriented distributed processing system
06/27/1991WO1991009440A1 Current control circuit
06/27/1991WO1991009378A1 Full-duplex video communication system
06/27/1991WO1991009367A1 Improvements in computer systems
06/27/1991DE3942390A1 Parallel bus link between sensors and data units - has identical connection to prevent faulty assembly and give variable bus length
06/27/1991CA2047737A1 Object oriented distributed processing system
06/26/1991EP0434267A2 Shared hardware interrupt circuit for personal computers
06/26/1991EP0434228A1 Data communications system
06/26/1991EP0434083A2 Data transfer system and method of transferring data
06/26/1991EP0433818A2 Method for configuring a computer bus adapter circuit board without the use of jumpers or switches
06/26/1991EP0433520A1 Elastic configurable buffer for buffering asynchronous data
06/26/1991CN1052563A Apparatus for conditioning priority arbitration
06/26/1991CN1052562A Main storage memory cards having single bit set and reset functions
06/25/1991US5027348 Method and apparatus for dynamic data block length adjustment
06/25/1991US5027316 Versioning of message formats in a 24-hour operating environment
06/25/1991US5027269 Method and apparatus for providing continuous availability of applications in a computer network
06/25/1991US5027089 High frequency noise bypassing
06/20/1991DE3941880A1 Data transmission procedure for vehicle electronics - using logic unit to coordinate transfer between units with different clock rates
06/19/1991EP0433078A2 Data transfer method and apparatus
06/19/1991EP0433077A2 Data transfer method
06/19/1991EP0432978A2 Apparatus for conditioning priority arbitration in buffered direct memory addressing
06/19/1991EP0432799A2 DMA Controller performing data transfer by 2-bus cycle transfer manner
06/19/1991EP0432582A1 Differential bus with specified default value
06/19/1991EP0432575A2 Data processor having wait state control unit
06/19/1991EP0432463A2 Distributed fair arbitration scheme for providing access to a data communication bus
06/18/1991US5025415 Memory card
06/18/1991US5025414 Serial bus interface capable of transferring data in different formats
06/18/1991US5025412 Universal bus interface
06/18/1991US5025370 Circuit for preventing lock-out of high priority requests to a system controller
06/18/1991US5025367 Storage allocation and garbage collection using liberate space tokens
06/18/1991CA1285078C Serial data direct memory access system
06/18/1991CA1285077C High speed interconnect unit for digital data processing system
06/15/1991CA2019019A1 Method and system for high speed data transfer
06/15/1991CA2019018A1 Method for high speed data transfer
06/12/1991EP0432076A2 High performance shared main storage interface
06/12/1991EP0431983A2 Communication and control system
06/12/1991EP0431982A2 Digital IC device arrangement
06/12/1991EP0431949A2 Data processing system with channel control means
06/12/1991EP0431688A1 Data transfer apparatus
06/12/1991EP0431683A1 Serial bus clock device
06/12/1991EP0431641A2 Microprocessor and method for setting up its peripheral functions
06/12/1991EP0431588A1 Token level judging device comprising a small amount of hardware
06/12/1991EP0431434A2 Data interface system
06/12/1991EP0431312A2 Multiprocessor interrupt control
06/12/1991EP0431231A1 Generation monitor system for customizing a data communication network
06/12/1991EP0396589A4 Method and apparatus for automatic loading of a data set in a node of a communication network
06/12/1991CN1052202A 可编程中断控制器 Programmable Interrupt Controller
06/12/1991CN1052201A Mehtods and apparatus for dynamically managing input/output (i/o) connectivity
06/11/1991US5023870 Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system
06/11/1991US5023867 Protocol and apparatus for selectively scanning a plurality of lines connected to a communication device
06/11/1991US5023829 Data transfer system having a channel adapter with varying data transfer lengths
06/11/1991US5023823 Multiple channel communications system and packaging configuration therefor
06/11/1991US5023774 Data I/O transaction method and system
06/11/1991US5023488 Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines
06/05/1991EP0430843A2 Method and apparatus for fault testing microprocessor address, data and control busses
06/05/1991EP0430727A1 Secure electronic mass-memory unit
06/05/1991EP0430673A2 Methods and apparatus for dynamically managing input/output (I/O) connectivity
06/05/1991EP0430500A2 System and method for atomic access to an input/output device with direct memory access
06/05/1991EP0429882A2 Low-end high-performance switch subsystem architecture
06/05/1991EP0429787A2 Data transfer apparatus
06/05/1991EP0429786A2 Data synchronizing buffer
06/05/1991CN1052003A Extended addressing using sub-addressed segment register
06/05/1991CN1051994A Bus master interface circuit with transparent preemption of data transfer operation
06/04/1991US5022077 Apparatus and method for preventing unauthorized access to BIOS in a personal computer system
06/04/1991US5022059 Counter circuit presettable with a plurality of count values
06/04/1991US5022004 Method and apparatus for DRAM memory performance enhancement
06/04/1991US5021950 Multiprocessor system with standby function
06/04/1991US5021942 Data processing system with packets specifying functions and arguments
05/1991
05/31/1991CA2013668A1 Method for input output configuration in a programmable logic controller
05/29/1991EP0429305A2 Data processing system including a plurality of data processing devices operating in parallel
05/29/1991EP0429054A2 Data representation and protocol
05/29/1991EP0428917A2 Internal cache microprocessor slowdown circuit with minimal system latency
05/29/1991EP0428771A1 Bidirectional data transfer device
05/29/1991EP0428535A1 Multilevel concurrent communications architecture for multiprocessor computer systems
05/29/1991CN1051802A Delay logic for preventing cpu lockout from bus ownership
05/29/1991CN1051801A Apparatus and method for guaranteeing strobe seperation timing
05/28/1991US5019966 Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data
05/28/1991US5019965 Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width