Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2006
12/05/2006US7145365 Logic processing apparatus, semiconductor device and logic circuit
12/05/2006US7145364 Self-bypassing voltage level translator circuit
12/05/2006US7145363 Level shifter
12/05/2006US7145362 Clock signal-distribution network for an integrated circuit
12/05/2006US7145361 Configurable integrated circuit with different connection schemes
12/05/2006US7145360 Configurable logic element with expander structures
12/05/2006US7145359 Multiple signal format output buffer
12/05/2006US7145170 Coupled superconducting charge quantum bit device and controlled-not gate using the same
11/2006
11/30/2006WO2006126436A1 Signal converting circuit
11/30/2006WO2006033681A3 Receiver circuit using nanotube-based switches and logic
11/30/2006US20060271901 Mixed-signal functions using R-cells
11/30/2006US20060267739 Device for comparing two words of n bits each
11/30/2006US20060267676 Voltage supply with low power and leakage current
11/30/2006US20060267634 Low voltage differential signaling receiver with a digital resistor unit and low voltage differential signaling interface system having the same
11/30/2006US20060267633 Pseudo-differential output driver with high immunity to noise and jitter
11/30/2006US20060267632 Method and apparatus for buffering bi-directional open drain signal lines
11/30/2006US20060267631 Interface device and information processing system
11/30/2006US20060267630 Semiconductor integrated circuit
11/30/2006US20060267629 Power gating techniques able to have data retention and variability immunity properties
11/30/2006US20060267628 Termination circuit and semiconductor device comprising that termination circuit
11/30/2006US20060267627 Semiconductor integrated circuit device
11/30/2006DE102005034345A1 Data processing method for use in e.g. digital computer, involves providing four different potential levels that comprise logic numbers, where binary logic gates and different trinary and quaternary logics are provided
11/29/2006EP1726094A1 Reconfigurable digital logic unit
11/29/2006EP1428155B1 Structures and methods for selectively applying a well bias to portions of a programmable device
11/29/2006CN1870436A Signal alignment circuit, drawing down circuit and pulling up circuit
11/29/2006CN1870435A Multiple data rates in programmable logic device serial interface
11/29/2006CN1287528C Semiconductor integrated circuit
11/29/2006CN1287523C Low current lost waiting state circuit for converting differential signal into single signal
11/29/2006CN1287520C Current driver circuit
11/28/2006US7143381 Resonance reduction arrangements
11/28/2006US7142478 Clock stop detector
11/28/2006US7142055 Buffer circuit and driver IC
11/28/2006US7142035 Signal generator circuit and level shifter with signal generator circuit
11/28/2006US7142033 Differential clocking scheme in an integrated circuit having digital multiplexers
11/28/2006US7142022 Clock enable buffer for entry of self-refresh mode
11/28/2006US7142021 Data inversion circuits having a bypass mode of operation and methods of operating the same
11/28/2006US7142020 Resonant logic and the implementation of low power digital integrated circuits
11/28/2006US7142019 System and method for reducing power-on transient current magnitude
11/28/2006US7142018 Circuits and methods for detecting and assisting wire transitions
11/28/2006US7142017 High-voltage-tolerant feedback coupled I/O buffer
11/28/2006US7142016 Input buffer of differential amplification type in semiconductor device
11/28/2006US7142015 Fast turn-off circuit for controlling leakage
11/28/2006US7142013 One-level zero-current-state exclusive or (XOR) gate
11/28/2006US7142012 Architecture and interconnect scheme for programmable logic circuits
11/28/2006US7142011 Programmable logic device with routing channels
11/28/2006US7142010 Programmable logic device including multipliers and configurations thereof to reduce resource utilization
11/28/2006US7142009 Adaptive power supply voltage regulation for programmable logic
11/28/2006US7142008 Method and apparatus for clock division on a programmable logic device
11/28/2006US7142007 Low power digital adaptive termination network
11/28/2006US7142004 Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method
11/28/2006US7141814 Input circuit
11/23/2006WO2006124953A2 Systems and methods for programming large-scale field-programmable analog arrays
11/23/2006WO2006124576A2 Integrated circuit with signal bus formed by cell abutment of logic cells
11/23/2006WO2006123584A1 Level shifter, shift register having the same, and display apparatus using the same
11/23/2006WO2006122746A2 Loosely-biased heterogeneous reconfigurable arrays
11/23/2006US20060261878 Method and apparatus switching a semiconductor switch with a multi-stage drive circuit
11/23/2006US20060261859 Semiconductor integrated circuit device
11/23/2006US20060261858 Circuit arrangement and method for processing a dual-rail signal
11/23/2006US20060261857 Integrated Circuit Dynamic Parameter Management In Response to Dynamic Energy Evaluation
11/23/2006US20060261856 Semiconductor chip and semiconductor device incorporating the same
11/23/2006US20060261855 Integrated circuit with signal bus formed by cell abutment of logic cells
11/23/2006US20060261854 Large scale integrated circuit
11/23/2006US20060261853 Output buffer strength trimming
11/23/2006US20060261852 Variable drive module for driving a load
11/23/2006US20060261851 Voltage conversion circuit with stable transition delay characteristic
11/23/2006US20060261850 Capacitively-coupled level restore circuits for low voltage swing logic circuits
11/23/2006US20060261849 Low-leakage level shifter with integrated firewall and method
11/23/2006US20060261848 Tristate startup operating mode setting device
11/23/2006US20060261847 Semiconductor integrated circuit device
11/23/2006US20060261846 Systems and methods for programming large-scale field-programmable analog arrays
11/23/2006US20060261845 Circuit for compensating for the declination of balanced impedance elements and a frequency mixer
11/23/2006US20060261844 Impedance control circuit in semiconductor device and impedance control method
11/23/2006DE102005022763A1 Electronic circuit, circuit arrangement and production process with multi-gate functional FET and protective FET having a charge-reducing transistor and a low trigger voltage
11/23/2006CA2608323A1 Integrated circuit with signal bus formed by cell abutment of logic cells
11/22/2006EP1723723A1 Logic basic cell, logic basic cell array and logic device
11/22/2006CN1868124A System and method for dynamically executing a function in a programmable logic array
11/22/2006CN1866743A Low-power routing multiplexers
11/22/2006CN1866739A Delay circuit and semiconductor device including same
11/22/2006CN1286270C CMOS reverse circuit and DC shift detecting circuit
11/22/2006CN1286269C Integrated circuit and battery powered electronic device
11/22/2006CN1286268C Current switching circuit
11/22/2006CN1286183C Multi-threshold MIS integrated circuit device and circuit designing method
11/21/2006US7139995 Integration of a run-time parameterizable core with a static circuit design
11/21/2006US7139956 Semiconductor integrated circuit device and test method thereof
11/21/2006US7138854 Integrated circuit delivering logic levels at a voltage independent from the mains voltage, with no attached regulator for the power section, and corresponding communication module
11/21/2006US7138852 Semiconductor integrated circuit device
11/21/2006US7138851 Semiconductor integrated circuit apparatus
11/21/2006US7138847 Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
11/21/2006US7138836 Hot carrier injection suppression circuit
11/21/2006US7138834 Symmetric differential logic circuits
11/21/2006US7138833 Selector circuit
11/21/2006US7138832 Nanotube-based switching elements and logic circuits
11/21/2006US7138831 Level conversion circuit and serial/parallel conversion circuit with level conversion function
11/21/2006US7138830 Supply enabled optimization output buffer
11/21/2006US7138829 Measuring input setup and hold time using an input-output block having a variable delay line
11/21/2006US7138828 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
11/21/2006US7138827 Programmable logic device with time-multiplexed interconnect
11/21/2006US7138826 Self-rewinding circuit
11/21/2006US7138825 Charge recycling power gate
11/21/2006US7138822 Integrated circuit and method of improving signal integrity