Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2007
03/14/2007EP1716640A4 Programmable logic circuit control apparatus, programmable logic circuit control method and program
03/14/2007CN1929307A N-domino output latch
03/14/2007CN1929306A P-domino register
03/14/2007CN1929305A Low-voltage differential signal driver circuit
03/14/2007CN1305219C Level shift circuit
03/14/2007CN1305218C Semiconductor device4
03/14/2007CN1305217C Hysteresis circuit used for comparator
03/14/2007CN1305000C Power management controlling system and method of pipeline structure
03/13/2007USRE39510 FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections
03/13/2007US7191427 Method for mapping a logic circuit to a programmable look up table (LUT)
03/13/2007US7191348 Transition detection at input of integrated circuit device
03/13/2007US7191339 System and method for using a PLD identification code
03/13/2007US7191333 Method and apparatus for calculating a multiplicative inverse of an element of a prime field
03/13/2007US7191205 Function block
03/13/2007US7191087 Sensor controller
03/13/2007US7190906 Linear full-rate phase detector and clock and data recovery circuit
03/13/2007US7190755 Phase-locked loop circuitry for programmable logic devices
03/13/2007US7190342 Shift register and display apparatus using same
03/13/2007US7190209 Low-power high-performance integrated circuit and related methods
03/13/2007US7190208 Self-oscillating full bridge driver IC
03/13/2007US7190206 Interface circuit and signal clamping circuit using level-down shifter
03/13/2007US7190204 Logical circuit
03/13/2007US7190193 Method and apparatus for a differential driver with voltage translation
03/13/2007US7190192 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
03/13/2007US7190190 Programmable logic device with on-chip nonvolatile user memory
03/13/2007US7190188 Signal transmission system, and signal transmission line
03/08/2007WO2007027833A2 Circuit, system and multiplexing signals with reduced jitter
03/08/2007WO2007009038A3 Interface for a multi-differential communication channel
03/08/2007US20070055907 Self-reparable semiconductor and method thereof
03/08/2007US20070055906 Self-reparable semiconductor and method thereof
03/08/2007US20070055845 Self-reparable semiconductor and method thereof
03/08/2007US20070055410 Control device, control method, and computer product
03/08/2007US20070052448 Electronic circuit with a chain of processing elements
03/08/2007US20070052447 CMOS buffer circuits and integrated circuits using the same
03/08/2007US20070052446 Driver circuit
03/08/2007US20070052445 Pre-buffer level shifter and input/output buffer apparatus
03/08/2007US20070052444 Programmable interconnect structures
03/08/2007US20070052443 Buffer circuit
03/08/2007US20070052442 Redundancy circuits hardened against single event upsets
03/08/2007US20070052441 Superconducting circuit for generating pulse signal
03/08/2007DE10111634B4 Elektrische Kompensationsschaltung zur Signallaufzeitbeeinflussung von integrierten elektronischen Bausteinen Electrical compensation circuit for signal propagation time influence of integrated electronic modules
03/07/2007EP1760889A2 High speed input circuit
03/07/2007EP1760888A2 Redundancy circuits hardened against single event upsets
03/07/2007EP1760887A2 Circuits and methods for cancelling signal dependent capacitance
03/07/2007EP1759460A1 Adaptive control of power supply for integrated circuits
03/07/2007EP1759250A1 Control scheme for binary control of a performance parameter
03/07/2007EP1346478A4 Architecture for field programmable gate array
03/07/2007CN2877146Y Logic input/output device for automatic guiding vehicle
03/07/2007CN1925328A Shift down level shift circuit
03/07/2007CN1925327A 半导体集成电路 The semiconductor integrated circuit
03/07/2007CN1303761C Digital potential converter and integrated circuit thereof
03/07/2007CN1303613C Semiconductor memory for reducing current loss when keeping data mode
03/06/2007US7188266 Systems and methods for reducing static and total power consumption in a programmable logic device
03/06/2007US7188265 Method of recognizing a card using a select signal during a determination mode and switching from low to high resistance after the determination
03/06/2007US7187991 Failsafe control circuit for electrical appliances
03/06/2007US7187709 High speed configurable transceiver architecture
03/06/2007US7187212 System and method for providing a fast turn on bias circuit for current mode logic transmitters
03/06/2007US7187211 P-domino output latch
03/06/2007US7187210 P-domino register
03/06/2007US7187209 Non-inverting domino register
03/06/2007US7187208 Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer
03/06/2007US7187207 Leakage balancing transistor for jitter reduction in CML to CMOS converters
03/06/2007US7187206 Power savings in serial link transmitters
03/06/2007US7187205 Integrated circuit storage element having low power data retention and method therefor
03/06/2007US7187204 Circuit for inspecting semiconductor device and inspecting method
03/06/2007US7187203 Cascadable memory
03/06/2007US7187202 Circuit for reducing programmable logic pin counts for large scale logic
03/06/2007US7187201 Programmable logic device suitable for implementation in molecular electronics
03/06/2007US7187200 Columnar architecture
03/06/2007US7187199 Structures and methods for testing programmable logic devices having mixed-fabric architectures
03/06/2007US7187198 Programmable logic device
03/06/2007US7187197 Transmission line driver
03/06/2007US7187196 Low rise/fall skewed input buffer compensating process variation
03/06/2007US7187195 Parallel compression test circuit of memory device
03/06/2007US7187016 Semiconductor device
03/01/2007WO2007023551A1 Semiconductor integrated circuit and its fabrication method
03/01/2007WO2006100455A3 Circuit and method for storing data in operational and sleep modes
03/01/2007WO2005114667A3 Internal voltage generator scheme and power management method
03/01/2007WO2005101254A3 High speed transient immune differential level shifting device
03/01/2007US20070047343 Automation of fuse compression for an asic design system
03/01/2007US20070046336 Thin film transistor array substrate
03/01/2007US20070046335 Programmable driver delay
03/01/2007US20070046334 Universal single-ended parallel bus
03/01/2007US20070046333 Differential output circuit with stable duty
03/01/2007US20070046332 Output buffer circuit
03/01/2007US20070046331 Output driver robust to data dependent noise
03/01/2007US20070046330 CMOS circuits with reduced crowbar current
03/01/2007US20070046329 Differential duty cycle restoration
03/01/2007US20070046328 Self-excited inverter circuit
03/01/2007US20070046327 Shift register circuit
03/01/2007US20070046326 Circuit and circuit connecting method
03/01/2007US20070046325 System-on-a-chip integrated circuit including dual-function analog and digital inputs
03/01/2007US20070046324 Sharing a static random-access memory (SRAM) table betweeen two or more lookup tables (LUTs) that are equivalent to each other
02/2007
02/28/2007CN1922786A Voltage clamp circuit, switching power supply apparatus, semiconductor integrated circuit device, and voltage level converting circuit
02/28/2007CN1921314A Grid electrode control circuit of up-draw transistor for high-voltage input
02/28/2007CN1921313A Grid electrode control circuit of up-draw transistor for high-voltage input
02/28/2007CN1921306A Differential clock generating device and related method
02/28/2007CN1920589A Interface circuit coupling semiconductor test apparatus with tested semiconductor device
02/28/2007CN1302453C Bias potential generating device
02/27/2007US7185307 Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units