Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
01/2007
01/25/2007US20070018694 High-speed cml circuit design
01/25/2007US20070018693 Cml circuit devices having improved headroom
01/25/2007US20070018692 SCL type FPGA with multi-threshold transistors and method for forming same
01/25/2007US20070018691 Multi-pad structure for semiconductor device
01/25/2007US20070018690 Maskable dynamic logic
01/25/2007US20070018689 High performance clock-powered logic
01/25/2007US20070018688 Digital Logic Unit
01/25/2007US20070018687 Line driver with reduced interference
01/25/2007US20070018686 Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver
01/25/2007US20070018685 Multi-stage light emitting diode driver circuit
01/25/2007US20070018684 Temperature-compensated output buffer
01/25/2007US20070018683 Signal transmitting device suited to fast signal transmission
01/25/2007US20070018682 Method and apparatus for calibrating driver impedance
01/25/2007US20070018681 Pin electronics driver
01/25/2007US20070018508 Method and apparatus for mode selection for high voltage integrated circuits
01/24/2007EP1746727A2 Multi-channel communication circuitry for programmable logic device integrated circuits and the like
01/24/2007EP1746481A2 Modular interconnect circuitry for multi-channel transceiver clock signals
01/24/2007EP1745549A1 Architecture and methods for computing with nanometer scale reconfigurable resistor crossbar switches
01/24/2007EP1745548A2 Low swing current mode logic family
01/24/2007EP1331671B1 Point contact array and electronic circuit comprising the same
01/24/2007CN1902822A Noise-tolerant signaling schemes supporting simplified timing and data recovery
01/24/2007CN1901374A Differential cascode current mode driver
01/24/2007CN1901369A 半导体集成电路器件 The semiconductor integrated circuit device
01/24/2007CN1297069C Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
01/23/2007US7168052 Yield driven memory placement system
01/23/2007US7167534 Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data
01/23/2007US7167039 Memory device having an adjustable voltage swing setting
01/23/2007US7167038 Power efficiency control output buffer
01/23/2007US7167036 Circuit for transforming signals varying between different voltages
01/23/2007US7167033 Data retaining circuit
01/23/2007US7167027 Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage
01/23/2007US7167026 Tri-state circuit using nanotube switching elements
01/23/2007US7167025 Non-sequentially configurable IC
01/23/2007US7167024 Methods and circuitry for implementing first-in first-out structure
01/23/2007US7167023 Multiple data rate interface architecture
01/23/2007US7167022 Omnibus logic element including look up table based logic elements
01/23/2007US7167020 Apparatus and method of tuning a digitally controlled input/output driver
01/23/2007US7167017 Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion in a power-up mode
01/23/2007US7167016 Operation mode setting circuit
01/23/2007US7166932 Power circuit
01/18/2007US20070013429 Clamping circuit to counter parasitic coupling
01/18/2007US20070013413 High-density logic techniques with reduced-stack multi-gate field effect transistors
01/18/2007US20070013412 Semiconductor device having super junction structure and method for manufacturing the same
01/18/2007US20070013411 Apparatus and methods for programmable slew rate control in transmitter circuits
01/18/2007US20070013410 Integrated receiver circuit
01/18/2007DE10035136B4 Integrierte Halbleiterschaltung und Verfahren zum Erzeugen eines Steuersignals dafür A semiconductor integrated circuit and method for generating a control signal for
01/17/2007EP1744459A2 Apparatus and methods for low-power routing in programmable logic devices
01/17/2007EP1744458A1 Apparatus and methods for programmable slew rate control in transmitter circuits
01/17/2007EP1743424A1 Ac coupling and gate charge pumping for nmos and pmos device control
01/17/2007EP1743422A2 Low leakage and data retention circuitry
01/17/2007CN1898870A Level shift circuit and semiconductor integrated circuit having the same
01/17/2007CN1898869A Load-aware circuit arrangement
01/17/2007CN1898868A Signal output circuit and power source voltage monitoring device using the same
01/17/2007CN1897462A Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
01/17/2007CN1897284A Semiconductor devices
01/17/2007CN1897098A 显示装置 Display device
01/17/2007CN1295879C Implementation of wide multiplexers in reconfigurable logic
01/17/2007CN1295878C Logical circuit and semiconductor device
01/17/2007CN1295877C Multi-mode I/O circuitry supporting low interference signaling schemes for high speed digital interfaces
01/17/2007CN1295876C Magnetic logic elements
01/17/2007CN1295875C Sample level shift circuit, two phase and multi-phase developing circuit and display
01/17/2007CN1295872C Semiconductor device
01/16/2007USRE39469 Semiconductor integrated circuit with mixed gate array and standard cell
01/16/2007US7165230 Switch methodology for mask-programmable logic devices
01/16/2007US7165074 Software development test case analyzer and optimizer
01/16/2007US7164744 Nanotube-based logic driver circuits
01/16/2007US7164414 Driving method of an electric circuit
01/16/2007US7164305 High-voltage tolerant input buffer circuit
01/16/2007US7164299 Output buffer circuit having pre-emphasis function
01/16/2007US7164294 Method for forming programmable logic arrays using vertical gate transistors
01/16/2007US7164293 Dynamic latch having integral logic function and method therefor
01/16/2007US7164292 Reducing electrical noise during bus turnaround in signal transfer systems
01/16/2007US7164291 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors
01/16/2007US7164290 Field programmable gate array logic unit and its cluster
01/16/2007US7164288 Electronic circuit with array of programmable logic cells
01/16/2007US7164287 Semiconductor device
01/16/2007US7164286 Device and method for matching output impedance in signal transmission system
01/11/2007WO2007006020A1 Elastic pipeline latch
01/11/2007WO2007005476A1 A dynamic circuit latch
01/11/2007WO2007004294A1 Level converter circuit, control method thereof, and electronic circuit
01/11/2007US20070008014 Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices
01/11/2007US20070008013 Universal programmable logic gate and routing method
01/11/2007US20070008012 Scannable dynamic circuit latch
01/11/2007US20070008011 Distributed power and clock management in a computerized system
01/11/2007US20070008010 High voltage integrated circuit driver with a high voltage PMOS bootstrap diode emulator
01/11/2007US20070008009 Source driver for controlling a slew rate and a method for controlling the slew rate
01/11/2007US20070008008 Data Output Device and Method of Semiconductor Device
01/11/2007US20070008007 Input/output circuit device
01/11/2007US20070008006 Output driver in semiconductor device
01/11/2007US20070008005 Integrated circuit device including interface circuit and electronic apparatus
01/11/2007US20070008004 Apparatus and methods for low-power routing circuitry in programmable logic devices
01/11/2007US20070008003 Self-biased high speed level shifter circuit
01/11/2007US20070008002 High-speed differential receiver
01/11/2007US20070008001 Cascadable level shifter cell
01/11/2007US20070008000 Passgate structures for use in low-voltage applications
01/11/2007US20070007999 Systems and methods for programming floating-gate transistors
01/11/2007US20070007998 System and method for configuring a field programmable gate array
01/11/2007US20070007997 Charge recycling power gate
01/11/2007US20070007996 A Method and Apparatus for Reducing Leakage in Integrated Circuits
01/11/2007US20070007995 Physical layers