Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2007
12/18/2007US7310004 Apparatus and method of interconnecting nanoscale programmable logic array clusters
12/18/2007US7310003 Configurable IC with interconnect circuits that have select lines driven by user signals
12/18/2007US7309908 Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device
12/18/2007US7309888 Spin based electronic device
12/13/2007WO2007105170A3 Electronic device and integrated circuit
12/13/2007US20070285979 Dynamic ram storage techniques
12/13/2007US20070285861 Over-voltage protection circuit and method thereof
12/13/2007US20070285184 Fully Integrated Tuneable Spin Torque Device For Generating An Oscillating Signal And Method For Tuning Such Apparatus
12/13/2007US20070285135 Output drive circuit that accommodates variable supply voltages
12/13/2007US20070285131 Sense amplifier circuit and sense amplifier-based flip-flop having the same
12/13/2007US20070285130 Floating driving circuit
12/13/2007US20070285129 Signal transmitting circuit
12/13/2007US20070285128 Differential line termination technique
12/13/2007US20070285127 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
12/13/2007US20070285126 Architecture for routing resources in a field programmable gate array
12/13/2007US20070285125 Method and Apparatus for Accessing Stored Data in a Reconfigurable IC
12/13/2007US20070285124 Embedding Memory Between Tile Arrangement of a Configurable IC
12/13/2007US20070285123 Programming semiconductor dies for pin map compatibility
12/13/2007US20070285122 On-Chip Supply Regulators
12/13/2007US20070285121 Reference voltage generators for reducing and/or eliminating termination mismatch
12/13/2007US20070285120 Configurable Voltage Mode Transmitted Architecture With Common-Mode Adjustment And Novel Pre-Emphasis
12/13/2007US20070285119 Combinatorial Logic Circuit
12/13/2007US20070285118 Semiconductor integrated circuit device
12/13/2007US20070284619 Semiconductor integrated circuit device
12/12/2007EP1865601A1 Asynchronous RS flip-flop having a test mode
12/12/2007EP1864199A2 Circuit and method for storing data in operational and sleep modes
12/12/2007EP1568134B1 Turn-on bus transmitter with controlled slew rate
12/12/2007EP1540659B1 A method and a unit for programming a memory
12/12/2007CN200990587Y LNB control circuit
12/12/2007CN101087140A Output interface circuit with small SSTL domain area
12/12/2007CN101087139A LVDS drive circuit for correcting signal swing rate
12/12/2007CN101087138A GTL output circuit with auxiliary charging circuit
12/12/2007CN101087128A Heat isolation access locket and its application in heat isolation CMOS time sequence circuit of no heat isolation gate
12/12/2007CN100355209C Waveform shaping circuit
12/12/2007CN100355208C Level shifter utilizing input controlled zero threshold blocking transistors
12/12/2007CN100355207C Gate driver with level shift between static wells with no power supply
12/12/2007CN100355206C Low power operation mechanism and method
12/12/2007CN100355193C 半导体集成电路器件 The semiconductor integrated circuit device
12/12/2007CN100354976C Non volatile storage device for high speed high efficiency changing in-site programmable door array function
12/11/2007US7308550 System for portable PLC configurations
12/11/2007US7308521 Multi-port communications integrated circuit and method for facilitating communication between a central processing chipset and multiple communication ports
12/11/2007US7307948 System with multiple path fail over, fail back and load balancing
12/11/2007US7307875 Spin based magnetic sensor
12/11/2007US7307822 Semiconductor integrated circuit apparatus
12/11/2007US7307465 Step-down voltage output circuit
12/11/2007US7307459 Programmable phase-locked loop circuitry for programmable logic device
12/11/2007US7307457 Apparatus for implementing dynamic data path with interlocked keeper and restore devices
12/11/2007US7307456 Automatic status assignment logic circuit apparatus for bay devices
12/11/2007US7307455 Buffer and organic light emitting display and a data driving circuit using the buffer
12/11/2007US7307453 Method and system for parallel state machine implementation
12/11/2007US7307452 Interconnect structure enabling indirect routing in programmable logic
12/11/2007US7307451 Field programmable gate array device
12/11/2007US7307449 Sub-cycle configurable hybrid logic/interconnect circuit
12/11/2007US7307448 Interconnectable nanoscale computational stages
12/06/2007WO2007137947A2 High-speed low-power integrated circuit interconnects
12/06/2007US20070279816 System to protect electrical fuses
12/06/2007US20070279403 Pixel circuit and display device
12/06/2007US20070279100 Recycling Charge to Reduce Energy Consumption During Mode Transition in Muiltithreshold Complementary Metal-Oxide-Semiconductor (MTCMOS) Circuits
12/06/2007US20070279099 Transceiver and method of operating an electrical circuit
12/06/2007US20070279098 Low-voltage differential signal driver for high-speed digital transmission
12/06/2007US20070279097 High-speed low-power integrated circuit interconnects
12/06/2007US20070279096 USB 2.0 Transmitter Using Only 2.5 Volt CMOS Devices
12/06/2007US20070279095 Low-voltage differential signal driver for high-speed digital transmission
12/06/2007US20070279094 Low-voltage differential signal driver for high-speed digital transmission
12/06/2007US20070279093 Level shift circuit and display device having the same
12/06/2007US20070279092 Level shifter circuit
12/06/2007US20070279090 Logic Basic Cell
12/06/2007US20070279089 Reconfigurable integrated circuits with scalable architecture including one or more adders
12/06/2007US20070279088 T-switch buffer, in particular for FPGA architectures
12/06/2007US20070279087 Reconfigurable integrated circuit device to automatically configure an initialization circuit
12/06/2007US20070279086 Antifuse programming circuit with snapback select transistor
12/06/2007US20070279085 Programmable Logic Circuit
12/06/2007US20070279084 Integrated circuit with graduated on-die termination
12/06/2007US20070279083 Buffer circuit with output signal slope control means
12/06/2007US20070279082 Semiconductor integrated circuit
12/06/2007DE102006025432A1 Logic arrangement e.g. dynamic random access memory module, operating method, involves arranging portion of logic cells of one of logic blocks between two blocks such that portion of logic cells realizes repeater functionality
12/05/2007EP1863179A1 Level-converter circuit
12/05/2007EP1863178A2 Low-voltage differential signal driver for high-speed digital transmission
12/05/2007EP1863177A2 Recycling charge to reduce energy consumption during mode transition
12/05/2007EP1862911A1 Interface device
12/05/2007EP1861973A1 Current mode interface for off-chip high speed communication
12/05/2007EP1550192A4 System and method for application monitoring and automatic disaster recovery for high-availability
12/05/2007CN101084627A Semiconductor device and level shifting circuit
12/05/2007CN101083466A Embedding cycle, recursive control module in programmable integrated circuit
12/05/2007CN101083465A Logical status control circuit
12/05/2007CN101083464A Semiconductor integrated circuit including output circuit
12/05/2007CN101083463A Apparatus and method for bidirectional level conversion
12/05/2007CN101083258A 半导体器件 Semiconductor devices
12/05/2007CN100353668C System and method for reducing short circuit current in a buffer
12/05/2007CN100353667C Input buffer circuit for stabilizing logic converting point
12/05/2007CN100353666C Level shifting circuit between isolated systems
12/05/2007CN100353550C Integrated circuit equipment and system using said equipment
12/05/2007CN100353524C Logic processing apparatus, semiconductor device and logic circuit
12/04/2007US7305649 Automatic generation of a streaming processor circuit
12/04/2007US7305647 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
12/04/2007US7305646 Relocatable mixed-signal functions
12/04/2007US7305509 Method and apparatus for zero stub serial termination capacitor of resistor mounting option in an information handling system
12/04/2007US7304509 Impedance circuit, power supply device
12/04/2007US7304508 Method and apparatus for fast flip-flop
12/04/2007US7304507 Modular buffering circuitry for multi-channel transceiver clock and other signals
1 ... 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 ... 420