Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2008
03/13/2008US20080061836 Current Mirror and Parallel Logic Evaluation
03/13/2008US20080061834 Reconfigurable semiconductor intergrated circuit and processing assignment method for the same
03/13/2008US20080061833 Semiconductor device having a pseudo power supply wiring
03/13/2008US20080061832 Protection circuits and methods of protecting circuits
03/13/2008US20080061831 Slew rate controlled digital output buffer without resistors
03/13/2008US20080061830 Method, apparatus, and system providing power supply independent imager output driver having a constant slew rate
03/13/2008US20080061829 Methods and apparatus for reducing duty cycle distortion in a multiple-stage inverter
03/13/2008US20080061828 Inductor-tuned buffer circuit with improved modeling and design
03/13/2008US20080061827 Floating driving circuit
03/13/2008US20080061826 Signal History Controlled Slew-Rate Transmission Method and Bus Interface Transmitter
03/13/2008US20080061825 Cml to cmos signal converter
03/13/2008US20080061824 Variable Threshold Transistor For The Schottky FPGA And Multilevel Storage Cell Flash Arrays
03/13/2008US20080061823 Configurable ic's with logic resources with offset connections
03/13/2008US20080061822 Programmable system on a chip for power-supply voltage and current monitoring and control
03/13/2008US20080061821 Apparatus and methods for multi-gate silicon-on-insulator transistors
03/13/2008US20080061820 MOS linear region impedance curvature correction
03/13/2008US20080061818 Techniques For Providing Calibrated On-Chip Termination Impedance
03/13/2008US20080061817 Changing Chip Function Based on Fuse States
03/13/2008US20080061816 Production of Limited Lifetime Devices Achieved Through E-Fuses
03/13/2008DE19950361B4 Signalumwandlungsvorrichtung mit dynamisch einstellbarer Referenzspannung und Chipsatz, der diese enthält Signal conversion apparatus with a dynamically adjustable reference voltage and chipset, which contains these
03/13/2008CA2662604A1 Quantum bit variable coupling method, quantum computing circuit using the method, and variable coupler
03/12/2008CN101142743A Chucking system for nano-manufacturing
03/12/2008CN101142684A Schottky device
03/12/2008CN101141549A Concurrent correlated double sampling and analog-to-digital conversion
03/12/2008CN101140315A FPGA logical code downloading method under JTAG downloading mode and downloading system thereof
03/12/2008CN101140314A On-site programmable gate array wire laying channel verification method and system thereof
03/12/2008CN100375391C Double-usage of integrated circuit tube pin and signal switch over on the pin
03/12/2008CN100375390C Semiconductor circuit
03/12/2008CN100375389C Clamping circuit to counter parasitic coupling
03/12/2008CN100375388C Integrated circuit low leakage power circuitry for use with advanced CMOS process
03/11/2008US7343483 Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
03/11/2008US7343276 Recording media including code for estimating IC power consumption
03/11/2008US7342568 Shift register circuit
03/11/2008US7342423 Circuit and method for calculating a logical combination of two input operands
03/11/2008US7342422 Semiconductor device having super junction structure and method for manufacturing the same
03/11/2008US7342421 CMOS circuit arrangement
03/11/2008US7342420 Low power output driver
03/11/2008US7342419 Bidirectional current-mode transceiver
03/11/2008US7342418 Low voltage differential signal receiver
03/11/2008US7342417 Low-leakage level shifter with integrated firewall and method
03/11/2008US7342416 Tileable field-programmable gate array architecture
03/11/2008US7342415 Configurable IC with interconnect circuits that also perform storage operations
03/11/2008US7342414 Fast router and hardware-assisted fast routing method
03/11/2008US7342413 Programmable crossbar signal processor with input/output tip interconnection
03/11/2008US7342412 Device for controlling on die termination
03/11/2008US7342411 Dynamic on-die termination launch latency reduction
03/11/2008US7342291 Standby current reduction over a process window with a trimmable well bias
03/06/2008WO2008028012A1 Junction field effect transistor input buffer level shifting circuit
03/06/2008WO2008026413A1 Reconfiguration controller for optically reconfigurable gate array and its method
03/06/2008WO2008026284A1 Logic circuit
03/06/2008US20080054982 Low power level shifter and method thereof
03/06/2008US20080054979 Level shifting circuit, driving device, led print head, and image forming apparatus
03/06/2008US20080054974 High speed flip-flops and complex gates using the same
03/06/2008US20080054946 Semiconductor integrated circuit
03/06/2008US20080054945 Method and apparatus for loss-of-clock detection
03/06/2008US20080054944 Method and circuit for producing symmetrical output signals tolerant to input timing skew, output delay/slewrate-mismatch, and complementary device mismatch
03/06/2008US20080054943 Variable switching point circuit
03/06/2008US20080054942 Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal
03/06/2008US20080054941 Voltage level shifter circuit
03/06/2008US20080054940 Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement
03/06/2008US20080054939 Creating high-drive logic devices from standard gates with minimal use of custom masks
03/06/2008US20080054938 Microcontroller with low noise peripheral
03/06/2008US20080054936 Output circuit of semiconductor device and semiconductor device including thereof
03/06/2008US20080054935 Method and apparatus for output driver calibration, and memory devices and system embodying same
03/06/2008US20080054934 Cmos output driver
03/06/2008US20080054933 Scan chain in a custom electronic circuit design
03/06/2008DE112004002572T5 Nutzung von Rückmeldung zur Wahl der Übertragungsspannung Terms of feedback on the choice of the transmission power
03/05/2008EP1894339A2 Device forming a logic gate for detecting a logic error
03/05/2008EP1714367A4 Systems and methods that employ inductive current steering for digital logic circuits
03/05/2008EP1627470B1 Integrated circuit comprising an energy saving mode and method for operating said circuit
03/05/2008CN101136629A Driving circuit and driving method for charge pump
03/05/2008CN101136160A Images display systems and image display driving method
03/05/2008CN101135717A On-site programmable gate array duplex selector verification method
03/05/2008CN100373775C Dynamic logic register and signal output method thereof
03/05/2008CN100373604C High power MCM package
03/05/2008CN100373501C Semiconductor storage device and semiconductor integrated circuit device
03/04/2008US7340644 Self-reparable semiconductor and method thereof
03/04/2008US7339819 Spin based memory coupled to CMOS amplifier
03/04/2008US7339771 Electrostatic protection circuit
03/04/2008US7339429 Adjusting methods of arithmetic multiplying circuit, drive circuit, and phase margin
03/04/2008US7339421 Differential circuit and receiver with same
03/04/2008US7339411 Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets
03/04/2008US7339402 Differential amplifier with over-voltage protection and method
03/04/2008US7339401 Nanotube-based switching elements with multiple controls
03/04/2008US7339400 Interface port for electrically programmed fuses in a programmable logic device
03/04/2008US7339399 Anti-noise input/output impedance control of semiconductor circuit with reduced circuit size
03/04/2008US7339398 Driver impedance control apparatus and system
03/04/2008US7339397 Data output apparatus and method
03/04/2008US7339389 Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal
03/04/2008CA2399384C Supporting multiple fpga configuration modes using dedicated on-chip processor
02/2008
02/28/2008WO2008023402A1 Decode circuit
02/28/2008WO2007137947A3 High-speed low-power integrated circuit interconnects
02/28/2008US20080052569 Error detection on programmable logic resources
02/28/2008US20080052440 Integrated Circuit Memory Device and Signaling Method with Topographic Dependent Signaling
02/28/2008US20080052434 Integrated Circuit Device and Signaling Method with Topographic Dependent Equalization Coefficient
02/28/2008US20080049492 Spin Memory with Write Pulse
02/28/2008US20080049489 Multi-Bit Spin Memory
02/28/2008US20080048753 Differential Reshaping Circuit
02/28/2008US20080048725 Domino Circuit with Master and Slave (DUAL) Pull Down Paths
02/28/2008US20080048724 Low power output driver