| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 05/06/2008 | US7368938 Input termination circuitry with high impedance at power off |
| 05/06/2008 | US7368937 Input termination circuits and methods for terminating inputs |
| 05/06/2008 | US7368935 Tamper response system for integrated circuits |
| 05/06/2008 | US7368902 Impedance calibration for source series terminated serial link transmitter |
| 05/02/2008 | WO2008051932A2 High speed double data rate jtag interface |
| 05/02/2008 | WO2008050267A2 Power amplifier |
| 05/01/2008 | US20080100345 Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays |
| 05/01/2008 | US20080100344 Scannable dynamic logic latch circuit |
| 05/01/2008 | US20080100343 Source Driver and Level Shifting Apparatus Thereof |
| 05/01/2008 | US20080100342 Circuit arrangement comprising a level shifter and method |
| 05/01/2008 | US20080100341 Level shifter having single voltage source |
| 05/01/2008 | US20080100340 Low voltage complementary metal oxide semiconductor process tri-state buffer |
| 05/01/2008 | US20080100339 Configurable ic with routing circuits with offset connections |
| 05/01/2008 | US20080100338 Logic circuit apparatus |
| 05/01/2008 | US20080100337 Memory circuit, semiconductor device and read control method of memory circuit |
| 05/01/2008 | US20080100336 Hybrid Logic/Interconnect Circuit in a Configurable IC |
| 05/01/2008 | US20080100334 Impedance matching circuit and semiconductor memory device with the same |
| 05/01/2008 | US20080100333 Impedance matching circuit of semiconductor memory device |
| 04/30/2008 | EP1639708B1 Hybrid compensated buffer design |
| 04/30/2008 | CN201054141Y Adder |
| 04/30/2008 | CN101171750A Transmitting apparatus |
| 04/30/2008 | CN101171680A Electrostatic breakdown protection circuit and semiconductor integrated circuit device provided with same |
| 04/30/2008 | CN101170274A Control circuit with bottom potential shift device for transferring input signal and corresponding method |
| 04/30/2008 | CN101169926A Liquid crystal display device for reducing noise and drive device thereof |
| 04/30/2008 | CN101169466A On-spot programmable gate array configurable logic block validation method and system |
| 04/30/2008 | CN100385793C Hybrid compensated buffer and design method thereof |
| 04/30/2008 | CN100385361C Power source supply structure more than one group of power voltage for low power consumption applications |
| 04/29/2008 | US7366275 Output calibrator with dynamic precision |
| 04/29/2008 | US7365591 Voltage generating circuit |
| 04/29/2008 | US7365590 Semiconductor integrated circuit apparatus |
| 04/29/2008 | US7365576 Binary digital latches not using only NAND or NOR circuits |
| 04/29/2008 | US7365575 Gated clock logic circuit |
| 04/29/2008 | US7365574 General purpose delay logic |
| 04/29/2008 | US7365573 Mixed-voltage interface and semiconductor integrated circuit |
| 04/29/2008 | US7365572 Multipath input buffer circuits |
| 04/29/2008 | US7365571 Input buffer with wide input voltage range |
| 04/29/2008 | US7365570 Pseudo-differential output driver with high immunity to noise and jitter |
| 04/29/2008 | US7365569 High-speed level shifter |
| 04/29/2008 | US7365568 Method and circuit for reducing programmable logic pin counts for large scale logic |
| 04/29/2008 | US7365567 Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop |
| 04/29/2008 | US7365566 Programmable logic circuit |
| 04/29/2008 | US7365565 Programmable system on a chip for power-supply voltage and current monitoring and control |
| 04/29/2008 | US7365564 Apparatus and method for controlling on die termination |
| 04/29/2008 | US7365563 Integrated circuit with performance compensation for process variation |
| 04/29/2008 | US7365431 Semiconductor device having multilayer structure and method for manufacturing thereof |
| 04/24/2008 | WO2008048282A2 Reconfigurable logic structures |
| 04/24/2008 | WO2008048280A2 Reconfigurable logic structures |
| 04/24/2008 | WO2008047323A1 Power amplifier |
| 04/24/2008 | WO2008046696A2 System for the flexible configuration of functional modules |
| 04/24/2008 | US20080098342 Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device |
| 04/24/2008 | US20080098203 Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry havingf fixed, application specific computational elements |
| 04/24/2008 | US20080094260 Logic circuit |
| 04/24/2008 | US20080094106 Apparatus for configuring I/O signal levels of interfacing logic circuits |
| 04/24/2008 | US20080094105 Programmable multiple supply regions with switched pass gate level converters |
| 04/24/2008 | US20080094104 High speed double data rate jtag interface |
| 04/24/2008 | US20080094103 Programmable Multiplexer |
| 04/24/2008 | US20080094102 Reprogrammable instruction DSP |
| 04/24/2008 | US20080094101 Programmable system on a chip for power-supply voltage and current monitoring and control |
| 04/24/2008 | US20080094099 Differential line compensation apparatus, method and system |
| 04/23/2008 | EP1914892A1 Output interface device with load compensation and corresponding electronic circuit |
| 04/23/2008 | EP1913695A2 Component with a functionally-configurable circuit arrangement |
| 04/23/2008 | EP1913410A2 Method and system for debug and test using replicated logic |
| 04/23/2008 | EP1573604A4 Integrated circuit with automatic pin-strapping configuration |
| 04/23/2008 | EP1092268B1 Interconnection and input/output resources for programmable logic integrated circuit devices |
| 04/23/2008 | CN101166028A Designing method, device and electronic device for semiconductor integrated circuit |
| 04/23/2008 | CN101166027A Level shift circuit |
| 04/23/2008 | CN101166026A Buffer circuit |
| 04/23/2008 | CN101166015A Circuit and method of reducing pop-up noise in a digital amplifier |
| 04/23/2008 | CN101165895A Signal generation and switching device and its method |
| 04/23/2008 | CN101165495A Method and apparatus for increasing clock frequency and data rate for semiconductor devices |
| 04/23/2008 | CN100383795C Configurable analog unit structure |
| 04/22/2008 | US7363564 Method and apparatus for securing communications ports in an electronic device |
| 04/22/2008 | US7363560 Circuit for and method of determining the location of a defect in an integrated circuit |
| 04/22/2008 | US7362652 Semiconductor circuit |
| 04/22/2008 | US7362144 Low jitter input buffer with small input signal swing |
| 04/22/2008 | US7362140 Low swing current mode logic family |
| 04/22/2008 | US7362139 Semiconductor device |
| 04/22/2008 | US7362138 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path |
| 04/22/2008 | US7362137 High speed voltage level shifter circuits |
| 04/22/2008 | US7362136 Dual voltage single gate oxide I/O circuit with high voltage stress tolerance |
| 04/22/2008 | US7362135 Apparatus and method for clock skew adjustment in a programmable logic fabric |
| 04/22/2008 | US7362134 Circuit and method for latch bypass |
| 04/22/2008 | US7362133 Three dimensional integrated circuits |
| 04/22/2008 | US7362132 Reconfigurable integrated circuit device to automatically configure an initialization circuit |
| 04/22/2008 | US7362131 Integrated circuit including programmable logic and external-device chip-enable override control |
| 04/22/2008 | US7362130 Method and device for transmission with reduced crosstalk |
| 04/22/2008 | US7362129 Methods of providing performance compensation for process variations in integrated circuits |
| 04/22/2008 | US7362128 Programmable impedance control circuit in semiconductor device and impedance range shifting method thereof |
| 04/22/2008 | US7362127 Driver circuit |
| 04/22/2008 | US7362125 Digital routing switch matrix for digitized radio-frequency signals |
| 04/17/2008 | US20080088359 Eased gate voltage restriction via body-bias voltage governor |
| 04/17/2008 | US20080088357 Semiconductor integrated circuit apparatus |
| 04/17/2008 | US20080088356 Semiconductor integrated circuit device |
| 04/17/2008 | US20080088345 Quad state logic design methods, circuits, and systems |
| 04/17/2008 | US20080088344 Automatic extension of clock gating technique to fine-grained power gating |
| 04/17/2008 | US20080088343 Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
| 04/17/2008 | US20080088342 Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications |
| 04/17/2008 | US20080088341 Level shifter circuit |
| 04/17/2008 | US20080088339 Hard Macro with Configurable Side Input/Output Terminals, for a Subsystem |
| 04/17/2008 | US20080088338 Semiconductor memory device for adjusting impedance of data output driver |