| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 01/02/2008 | EP1873918A1 Method of controlling the evaluation time of a state machine |
| 01/02/2008 | EP1873915A2 Secure input circuit with single channel peripheral connection for the input of a bus participant |
| 01/02/2008 | EP1873786A2 Thin film semiconductor device and manufacturing method |
| 01/02/2008 | EP1872475A1 Method for producing a time base for a microcontroller and circuit arrangement therefor |
| 01/02/2008 | EP1872288A2 Method and system for debugging using replicated logic and trigger logic |
| 01/02/2008 | CN101099358A Line driver with selectable power consumption |
| 01/02/2008 | CN101097778A Metallic oxide storage medium based programming unit multiplexed FPGA device |
| 01/02/2008 | CN101097694A Reference voltage generating circuit and liquid crystal display device using the same |
| 01/02/2008 | CN100359808C High-speed current mode logic circuit |
| 01/02/2008 | CN100359807C Terminal structure for high-speed high-pin density chip |
| 01/02/2008 | CN100359505C High speed differential pre-driver using common mode pre-charge |
| 01/01/2008 | US7315201 Methods and systems for reducing leakage current in semiconductor circuits |
| 01/01/2008 | US7315192 CMOS-based receiver for communications applications |
| 01/01/2008 | US7315188 Programmable high speed interface |
| 01/01/2008 | US7315186 Voltage mode driver with current mode equalization |
| 01/01/2008 | US7315183 Single-supply voltage translator input having low supply current |
| 01/01/2008 | US7315182 Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control |
| 12/27/2007 | WO2007149532A2 Compiler system, method and software for a resilient integrated circuit architecture |
| 12/27/2007 | WO2007149527A2 Fault tolerant integrated circuit architecture |
| 12/27/2007 | WO2007149517A2 Circuit and method for power management |
| 12/27/2007 | WO2007149495A2 Program binding system, method and software for a resilient integrated circuit architecture |
| 12/27/2007 | WO2007149494A2 Resilient integrated circuit architecture |
| 12/27/2007 | WO2007149472A2 Element controller for a resilient integrated circuit architecture |
| 12/27/2007 | WO2007148385A1 Digital circuit device |
| 12/27/2007 | US20070300202 Compact standard cell |
| 12/27/2007 | US20070297520 Noise-tolerant signaling schemes supporting simplified timing and data recovery |
| 12/27/2007 | US20070296482 Level-conversion circuit |
| 12/27/2007 | US20070296470 Semiconductor integrated circuit controlling output impedance and slew rate |
| 12/27/2007 | US20070296465 Domino logic testing systems and methods |
| 12/27/2007 | US20070296464 Methods and apparatus for serially connected devices |
| 12/27/2007 | US20070296463 Driver with variable output voltage and current |
| 12/27/2007 | US20070296462 Logic circuit for high-side gate driver |
| 12/27/2007 | US20070296461 System, method and apparatus for transmitting and receiving a transition minimized differential signal |
| 12/27/2007 | US20070296460 Semiconductor apparatus and signal processing system |
| 12/27/2007 | US20070296459 Resilient integrated circuit architecture |
| 12/27/2007 | US20070296458 Fault tolerant integrated circuit architecture |
| 12/27/2007 | US20070296457 Programmable Logic Circuit Control Apparatus, Programmable Logic Circuit Control Method and Program |
| 12/27/2007 | US20070296455 Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal |
| 12/27/2007 | US20070296395 Semiconductor device, semiconductor device testing method, and probe card |
| 12/27/2007 | DE102007019519A1 Verfahren und Vorrichtung zur Temperaturkompensation einer Chipausgangs-Treiberschaltung (OCD) Method and apparatus for temperature compensation of a chip output driver circuit (OCD) |
| 12/26/2007 | EP1442359A4 General purpose fixed instruction set (fis) bit-slice feedback processor unit/computer system |
| 12/26/2007 | CN101095232A Input stage resistant against negative voltage swings |
| 12/26/2007 | CN101093993A Voltage converter |
| 12/26/2007 | CN101093992A Input circuits and methods thereof |
| 12/26/2007 | CN100358240C Fail-safe method and circuit |
| 12/25/2007 | US7313742 Logic circuitry having self-test function |
| 12/25/2007 | US7313723 Self-reparable semiconductor and method thereof |
| 12/25/2007 | US7312643 Differential current driver and data transmission method |
| 12/25/2007 | US7312640 Semiconductor integrated circuit device having power reduction mechanism |
| 12/25/2007 | US7312639 Universal single-ended parallel bus |
| 12/25/2007 | US7312638 Scanning line driving circuit, display device, and electronic apparatus |
| 12/25/2007 | US7312637 Enhanced timing margin memory interface |
| 12/25/2007 | US7312636 Voltage level shifter circuit |
| 12/25/2007 | US7312635 Integrated circuit provided with core unit and input and output unit |
| 12/25/2007 | US7312634 Exclusive-or and/or exclusive-nor circuits including output switches and related methods |
| 12/25/2007 | US7312633 Programmable routing structures providing shorter timing delays for input/output signals |
| 12/25/2007 | US7312632 Fracturable lookup table and logic element |
| 12/25/2007 | US7312631 Structures and methods for avoiding hold time violations in a programmable logic device |
| 12/25/2007 | US7312630 Configurable integrated circuit with built-in turns |
| 12/25/2007 | US7312629 Programmable impedance control circuit calibrated at Voh, Vol level |
| 12/25/2007 | US7312627 Decoding circuit for on die termination in semiconductor memory device and its method |
| 12/25/2007 | US7312626 CMOS circuits with reduced crowbar current |
| 12/25/2007 | US7312517 System-in-package type semiconductor device |
| 12/25/2007 | US7312109 Methods for fabricating fuse programmable three dimensional integrated circuits |
| 12/21/2007 | WO2007146110A2 Tri-stated driver for bandwidth-limited load |
| 12/21/2007 | WO2007145864A2 Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
| 12/21/2007 | WO2007145843A2 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
| 12/21/2007 | WO2007145160A1 Data transmitting device and data transmitting method |
| 12/21/2007 | WO2007145086A1 Semiconductor device, signal transmitter and signal transmission method |
| 12/21/2007 | CA2654553A1 Tri-stated driver for bandwidth-limited load |
| 12/21/2007 | CA2653626A1 Circuit configurations having four terminal jfet devices |
| 12/20/2007 | US20070290752 Adjusting methods of arithmetic multiplying circuit, drive circuit, and phase margin |
| 12/20/2007 | US20070290720 P-domino register with accelerated non-charge path |
| 12/20/2007 | US20070290719 N-domino register with accelerated non-discharge path |
| 12/20/2007 | US20070290718 Semiconductor device |
| 12/20/2007 | US20070290716 Multiplexing circuit for decreasing output delay time of output signal |
| 12/20/2007 | US20070290715 Method And System For Using One-Time Programmable (OTP) Read-Only Memory (ROM) To Configure Chip Usage Features |
| 12/20/2007 | US20070290714 Calibration methods and circuits to calibrate drive current and termination impedance |
| 12/20/2007 | US20070290713 Input termination circuitry with high impedance at power off |
| 12/20/2007 | US20070290712 Switch selectable terminator for differential and pseudo-differential signaling |
| 12/20/2007 | US20070290711 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
| 12/19/2007 | EP1868293A1 Computer system, data structure showing configuration information, and mapping device and method |
| 12/19/2007 | EP1868292A1 P-domino register with accelerated non-charge path |
| 12/19/2007 | EP1868291A1 N-domino register with accelerated non-discharge path |
| 12/19/2007 | EP1868079A1 Csa 5-3 compressing circuit and carrier-save adding circuit using the same |
| 12/19/2007 | EP1867048A1 Electronic device |
| 12/19/2007 | EP1866816A1 Processing pedigree data |
| 12/19/2007 | CN101091314A 半导体集成电路 The semiconductor integrated circuit |
| 12/19/2007 | CN101090267A High linearity wide input range changable gain single quadrant CMOS multiplier |
| 12/19/2007 | CN101090266A Semiconductor device and electronic apparatus having the same |
| 12/19/2007 | CN100356690C Condition monitor system responsive to different input pulses |
| 12/19/2007 | CN100356687C Latch circuit |
| 12/19/2007 | CN100356674C 升压时钟生成电路及半导体装置 When the boost clock generation circuit and semiconductor device |
| 12/18/2007 | US7310795 Method and apparatus for simulating logic circuits that include a circuit block to which power is not supplied |
| 12/18/2007 | US7310757 Error detection on programmable logic resources |
| 12/18/2007 | US7310720 Method for portable PLC configurations |
| 12/18/2007 | US7310278 Method and apparatus for in-system redundant array repair on integrated circuits |
| 12/18/2007 | US7310008 Configurable delay chain with stacked inverter delay elements |
| 12/18/2007 | US7310007 Logic circuit, system for reducing a clock skew, and method for reducing a clock skew |
| 12/18/2007 | US7310006 Semiconductor integrated circuit |