Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
10/2007
10/25/2007US20070247192 Open drain output circuit
10/25/2007US20070247191 Pre-emphasis automatic adjusting method and data transmission system using same
10/25/2007US20070247190 Dual voltage single gate oxide I/O circuit with high voltage stress tolerance
10/25/2007US20070247189 Field programmable semiconductor object array integrated circuit
10/25/2007US20070247188 Programmable Semiconductor Device
10/25/2007US20070247187 Apparatus and method for remotely powering a data acquisition or utilization device
10/25/2007US20070247186 Semiconductor integrated circuits with power reduction mechanism
10/25/2007US20070247185 Memory system with dynamic termination
10/25/2007US20070247184 Serial communications bus with active pullup
10/25/2007US20070247183 Logic-latching apparatus for improving system-level electrostatic discharge robustness
10/25/2007US20070247182 Protection of security key information
10/24/2007EP1848001A1 Soft error location and sensitivity detection for programmable devices
10/24/2007EP1287615B1 Fpga lookup table with high speed read decoder
10/24/2007CN101060325A Storage medium for storing unit information bank and method of designing semiconductor integrated circuit
10/24/2007CN101060324A 一种差分信号接口电路 Kind of differential signal interface circuit
10/24/2007CN101060323A Clocked inverter, nand, nor and shift resister
10/24/2007CN101060322A Semiconductor integrated circuit
10/24/2007CN101060120A 半导体集成电路 The semiconductor integrated circuit
10/24/2007CN100345380C Fail-safe circuit for differential signal receiver in low voltage
10/23/2007US7286625 High-speed clock and data recovery circuit
10/23/2007US7286020 Techniques for monitoring and replacing circuits to maintain high performance
10/23/2007US7285986 High speed, low power CMOS logic gate
10/23/2007US7285985 Event-driven logic circuit
10/23/2007US7285984 Look-up table structure with embedded carry logic
10/23/2007US7285983 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
10/23/2007US7285982 Configuration circuits for programmable logic devices
10/23/2007US7285981 Configuration circuit for programmable logic devices
10/23/2007US7285980 Method and apparatus for multiplexing an integrated circuit pin
10/23/2007US7285978 Circuit and method for impedance calibration of output impedance of LVDS driver
10/23/2007US7285977 Impedance control circuits and methods of controlling impedance
10/23/2007US7285975 Termination providing apparatus mounted on memory module or socket and memory system using the apparatus
10/23/2007US7285974 Large scale integrated circuit
10/23/2007US7285487 Method and apparatus for network with multilayer metalization
10/18/2007WO2007118072A2 Apparatus and method for remotely powering a data acquisition or utilization device
10/18/2007WO2007117744A2 Electronic device and method
10/18/2007WO2007116378A2 Electronic circuit
10/18/2007WO2007115600A1 Packet-oriented communication in reconfigurable circuit(s)
10/18/2007US20070245289 Memory re-implementation for field programmable gate arrays
10/18/2007US20070242404 Circuit output stage protection system
10/18/2007US20070242021 Level shifter circuit and display device provided therewith
10/18/2007US20070241811 Methods and Systems for Reducing Leakage Current in Semiconductor Circuits
10/18/2007US20070241803 IO clamping circuit method utilizing output driver transistors
10/18/2007US20070241792 Apparatus for hysteresis based process compensation for cmos receiver circuits
10/18/2007US20070241791 Non-Sequentially Configurable IC
10/18/2007US20070241790 Semiconductor integrated circuit
10/18/2007US20070241789 Configurable Integrated Circuit with Offset Connection
10/18/2007US20070241788 VPA Logic Circuits
10/18/2007US20070241787 Configurable Circuits, IC's, and Systems
10/18/2007US20070241786 Configurable Integrated Circuit with Different Connection Schemes
10/18/2007US20070241785 Configurable ic's with logic resources with offset connections
10/18/2007US20070241784 Configurable ic with interconnect circuits that have select lines driven by user signals
10/18/2007US20070241783 Configurable ic with routing circuits with offset connections
10/18/2007US20070241782 Configurable IC with interconnect circuits that also perform storage operations
10/18/2007US20070241781 Variable width management for a memory of a configurable IC
10/18/2007US20070241780 Reconfigurable ic that has sections running at different reconfiguration rates
10/18/2007US20070241779 Semiconductor integrated circuit
10/18/2007US20070241778 IC with configurable storage circuits
10/18/2007US20070241777 Configurable Circuits, IC's and Systems
10/18/2007US20070241776 Configurable Logic Circuits with Commutative Properties
10/18/2007US20070241775 Storage elements for a configurable ic and method and apparatus for accessing data stored in the storage elements
10/18/2007US20070241774 Reconfigurable ic that has sections running at different looperness
10/18/2007US20070241773 Hybrid logic/interconnect circuit in a configurable ic
10/18/2007US20070241772 Embedding memory within tile arrangement of a configurable ic
10/18/2007US20070241771 Configurable circuits, IC's, and systems
10/18/2007US20070241770 Configurable integrated circuit with built-in turns
10/18/2007DE102006016514A1 Logic circuit e.g. dynamic programmable logic array, has NMOS-base transistor and two transistors, which are parallely arranged, where parameter of current flowing through NMOS-base transistor is determined by resistance values
10/17/2007EP1845623A2 Method and device
10/17/2007EP1845622A2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
10/17/2007EP1845619A1 Buffer circuit comprising means of controlling the mutual conductance of the output signal.
10/17/2007EP1776763A4 Integrated nanotube and field effect switching device
10/17/2007EP1495542B1 Circuit arrangement and method for generating a dual-rail output signal
10/17/2007CN101057403A Adiabatic cmos design
10/17/2007CN101057206A Latch-based serial port output buffer
10/17/2007CN101056103A Semiconductor integrated circuit device and substrate bias controlling method
10/17/2007CN101056102A Meter-checking computing circuit
10/17/2007CN101056101A Multiple data rate in serial interface for programmable logic device
10/17/2007CN101056100A Heterogeneous transceiver architecture for wide range programmability of programmable logic devices
10/17/2007CN101055915A Logic part and magnetic logic part array based on the dual potential base magnetic tunnel junction
10/17/2007CN101055306A Discharge time timing unit of electric power system and its method
10/17/2007CN100344063C Output stage resistant against high voltage swing
10/17/2007CN100344062C 电平移动器 Level shifter
10/17/2007CN100344061C Digital electronic circuit with low power consumption
10/17/2007CN100344058C Dual edge programmable delay unit and method for providing programm of the unit
10/16/2007US7284245 Query trees including or nodes for event filtering
10/16/2007US7283943 Method of modeling circuit cells for powergrid analysis
10/16/2007US7283116 Scan driver and scan driving system with low input voltage, and their level shift voltage circuit
10/16/2007US7282981 Level conversion circuit with improved margin of level shift operation and level shifting delays
10/16/2007US7282964 Circuit for detecting transitions on either of two signal lines referenced at different power supply levels
10/16/2007US7282961 Apparatus for hysteresis based process compensation for CMOS receiver circuits
10/16/2007US7282960 Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
10/16/2007US7282959 CMOS circuit including double-insulated-gate field-effect transistors
10/16/2007US7282958 Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal
10/16/2007US7282957 Semiconductor integrated circuit
10/16/2007US7282956 High voltage switching circuit of nonvolatile memory device
10/16/2007US7282955 Semiconductor memory device with on-die termination circuit
10/16/2007US7282954 Capacitor-coupled level shifter with duty-cycle independence
10/16/2007US7282953 Pre-buffer level shifter and input/output buffer apparatus
10/16/2007US7282952 Level shift circuit, electro-optical device using the same, and electronic apparatus
10/16/2007US7282951 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
10/16/2007US7282950 Configurable IC's with logic resources with offset connections
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