Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
08/2009
08/26/2009EP1709742B1 Pull-up circuit
08/26/2009CN101517545A Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
08/26/2009CN101515800A Low-jitter conversion circuit from CMOS to CML
08/26/2009CN101515799A Auto-detecting CMOS input circuit for single-voltage-supply cmos
08/26/2009CN100533980C LVDS drive circuit for correcting signal swing rate
08/26/2009CN100533979C GTL output circuit with auxiliary charging circuit
08/26/2009CN100533933C PWM driver circuit
08/26/2009CN100533533C Level conversion circuit, display device and cellular terminal apparatus
08/26/2009CN100533529C Electronic circuit, electrooptical device and electronic equipment
08/26/2009CN100533158C Method and device of providing impedance calibration for source series terminated serial link transmitter
08/25/2009US7579895 Clock-generator architecture for a programmable-logic-based system on a chip
08/25/2009US7579882 Output buffer circuit eliminating high voltage insulated transistor and level shift circuit, and an electronic device using the output buffer circuit
08/25/2009US7579875 Interface circuit and control method thereof
08/25/2009US7579873 Slew rate control circuit for small computer system interface (SCSI) differential driver
08/25/2009US7579872 Low-voltage differential signal driver for high-speed digital transmission
08/25/2009US7579871 Current drive circuit and method of boosting current using the same
08/25/2009US7579870 Level shifter
08/25/2009US7579869 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
08/25/2009US7579868 Architecture for routing resources in a field programmable gate array
08/25/2009US7579867 Restructuring data from a trace buffer of a configurable IC
08/25/2009US7579866 Programmable logic device with configurable override of region-wide signals
08/25/2009US7579865 Selective loading of configuration data into configuration memory cells
08/25/2009US7579864 Logic block control system and logic block control method
08/25/2009US7579863 Circuit and method for reducing pin count of chip
08/25/2009US7579862 MOS linear region impedance curvature correction
08/25/2009US7579861 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same
08/20/2009WO2009102572A1 Circuits and methods for sleep state leakage current reduction
08/20/2009WO2009100564A1 An integrated circuit with improved logic cells
08/20/2009WO2009075810A8 Avoiding floating diffusion contamination
08/20/2009WO2009067470A3 Charge recycling a 1 of n ndl gate with a time varying power supply
08/20/2009US20090210848 Logic array devices having complex macro-cell architecture and methods facilitating use of same
08/20/2009US20090207539 I/o circuit
08/20/2009US20090206937 Inverting cell
08/20/2009US20090206883 Thermal Electric NAND Gate
08/20/2009US20090206882 Thermal Electric NOR Gate
08/20/2009US20090206881 Semiconductor integrated circuit
08/20/2009US20090206880 Semiconductor integrated circuit
08/20/2009US20090206879 Signal transmission circuit and signal transmission system using the same
08/20/2009US20090206878 Level shift circuit for a driving circuit
08/20/2009US20090206877 Quad state logic design methods, circuits and systems
08/20/2009US20090206876 Programmable core for implementing logic change
08/20/2009US20090206875 Programmable io architecture
08/20/2009US20090206874 Semiconductor device
08/20/2009US20090206873 Data output driver
08/20/2009US20090206872 System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality
08/20/2009US20090206871 Arbitrary quantum operations with a common coupled resonator
08/20/2009DE19742162B4 Taktsignal-Steuervorrichtung für Datenausgabepuffer Clock signal control device for data output buffer
08/19/2009EP2091153A1 Voltage switching circuit
08/19/2009EP2091152A1 Digital signal output control device and assembly with numerous such digital signal output control devices
08/19/2009CN201294512Y Logic circuit and television set with the same
08/19/2009CN201294511Y Digital signal input device
08/19/2009CN101512983A Routing facilities for seabed electronic module
08/19/2009CN101512982A Routing facilities for seabed electronic module
08/19/2009CN101510776A FPGA wiring and programmable switch structure
08/19/2009CN101510775A Digital circuit capable of evolving and evolvement method
08/19/2009CN101510774A Mixing voltage output circuit
08/19/2009CN101510773A Level shift circuit for a driving circuit
08/19/2009CN101510772A Output/input circuit with small area
08/19/2009CN101510404A Grid line drive device of liquid crystal display and renovation method thereof
08/19/2009CN101510403A Grid line drive device of liquid crystal display
08/19/2009CN101510399A Driving circuits in electronic device
08/19/2009CN100530966C Receiver of low voltage difference signal
08/19/2009CN100530965C High performance level shift circuit with low input voltage
08/19/2009CN100530964C Signal generation circuit
08/19/2009CN100530594C Switch methodology for mask-programmable logic devices
08/18/2009US7577858 Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
08/18/2009US7577166 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
08/18/2009US7577055 Error detection on programmable logic resources
08/18/2009US7577012 Ferroelectric memory device, method for driving ferroelectric memory device, electronic apparatus, and method for driving electronic apparatus
08/18/2009US7576619 Integrated circuit arrangement
08/18/2009US7576568 Self-selecting precharged domino logic circuit
08/18/2009US7576567 Low-voltage differential signal driver for high-speed digital transmission
08/18/2009US7576566 Level-conversion circuit
08/18/2009US7576565 Crossbar waveform driver circuit
08/18/2009US7576564 Configurable IC with routing circuits with offset connections
08/18/2009US7576562 Diagnosable structured logic array
08/18/2009US7576560 Apparatus for measuring on-die termination (ODT) resistance and semiconductor memory device having the same
08/18/2009US7576559 USB device and data processing system having the same
08/18/2009US7576558 Apparatus and method for enhanced readback of programmable logic device state information
08/18/2009US7576557 Method and apparatus for mitigating one or more event upsets
08/18/2009US7576449 Method for converting direct voltage into three-phase alternating voltage
08/18/2009US7576353 Ballistic deflection transistor and logic circuits based on same
08/13/2009WO2009098626A1 Low-swing cmos input circuit
08/13/2009WO2009098153A1 Integrated circuit including a large number of identical elementary circuits powered in parallel
08/13/2009US20090201077 Clocked inverter, nand, nor and shift register
08/13/2009US20090201071 Bootstrap circuit
08/13/2009US20090201049 Integrated circuit with input and/or output bolton pads with integrated logic
08/13/2009US20090201046 Output buffer and method having a supply voltage insensitive slew rate
08/13/2009US20090201045 Input circuit and semiconductor integrated circuit comprising the input circuit
08/13/2009US20090201044 logic performance in cyclic structures
08/12/2009EP2088675A2 Antifuse reroute of dies
08/12/2009EP2087592A1 Logic output stage of integrated circuit protected against battery inversion
08/12/2009EP2087587A1 Power amplifier
08/12/2009EP1751763A4 Systems and methods for write protection of non-volatile memory devices
08/12/2009CN101507116A Dual mode AES implementation to support single and multiple AES operations
08/12/2009CN101507115A Semiconductor device and system and method of crystal sharing
08/12/2009CN101506976A N-channel ESD clamp with improved performance
08/12/2009CN101505148A CLB structure and CLB optimization method
08/12/2009CN101505147A System and apparatus for generating ideal rise and fall time
08/12/2009CN101504816A Signal-line driving circuit, display device and electronic equipments