Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
09/2009
09/30/2009CN101546545A Clock signal generating signal and clock signal generating circuit
09/30/2009CN101546536A Liquid crystal display having function of eliminating power-off ghost shadow
09/30/2009CN101546207A Clock signal switching circuit
09/30/2009CN100546190C Logical switch device for low electromagnetic interference
09/29/2009US7596775 Method for determining a standard cell for IC design
09/29/2009US7596774 Hard macro with configurable side input/output terminals, for a subsystem
09/29/2009US7596018 Spin memory with write pulse
09/29/2009US7595794 Circuit having source follower and semiconductor device having the circuit
09/29/2009US7595665 Clock gated circuit
09/29/2009US7595664 Repeater circuit having different operating and reset voltage ranges, and methods thereof
09/29/2009US7595663 Interface circuit
09/29/2009US7595662 Transmission/reception apparatus for differential signals
09/29/2009US7595661 Low voltage differential signaling drivers including branches with series resistors
09/29/2009US7595660 Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus
09/29/2009US7595659 Logic cell array and bus system
09/29/2009US7595658 Voltage divider circuit
09/29/2009US7595657 Dynamic dual control on-die termination
09/29/2009US7595656 Interface circuit and semiconductor integrated circuit
09/29/2009US7595655 Retrieving data from a configurable IC
09/29/2009US7595645 Calibration circuit and semiconductor device incorporating the same
09/29/2009US7595533 Thin film semiconductor device and manufacturing method
09/24/2009WO2009115979A1 Methods, circuits, systems and arrangements for undriven or driven pins
09/24/2009WO2008146299A3 An adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique
09/24/2009US20090237114 Decoder circuit
09/24/2009US20090237113 Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus
09/24/2009US20090237112 Data transfer cable for programmable logic devices
09/24/2009US20090237111 Integrated Circuits with Hybrid Planer Hierarchical Architecture and Methods for Interconnecting Their Resources
09/24/2009US20090237110 Programmable on-chip logic analyzer apparatus, systems, and methods
09/24/2009US20090237109 Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus
09/24/2009US20090237108 Semiconductor integrated circuit
09/24/2009US20090237107 Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same
09/24/2009US20090237106 Digital programmable phase generator
09/23/2009EP2104231A1 Circuit for generating a square wave pulse train
09/23/2009EP2102985A2 Circuit comprising a matrix of programmable logic cells
09/23/2009CN101542905A Inverter circuit
09/23/2009CN101542904A Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system
09/23/2009CN101540604A Loading wire of programmable logic device
09/23/2009CN101540603A Efficacy push-pull buffer circuit, system and method for high frequency signals
09/23/2009CN101540585A Amplifier
09/23/2009CN101540512A Multifunctional management module of double series lithium batteries
09/23/2009CN101540148A Driving device for liquid crystal display and related output enable signal transfer device
09/23/2009CN101540147A Liquid crystal display driving device with independent voltage conversion unit
09/23/2009CN101540146A Liquid crystal display driving device with interface conversion function
09/23/2009CN100544209C Logical status control circuit
09/23/2009CN100544208C Level translator circuit and display element drive circuit using same
09/23/2009CN100543872C Apparatus for adjusting slew rate in semiconductor memory device and method therefor
09/22/2009US7594046 Data processing in which concurrently executed processes communicate via a FIFO buffer
09/22/2009US7593499 Apparatus and method for low power routing of signals in a low voltage differential signaling system
09/22/2009US7592842 Configurable delay chain with stacked inverter delay elements
09/22/2009US7592841 Circuit configurations having four terminal JFET devices
09/22/2009US7592840 Domino circuit with disable feature
09/22/2009US7592839 Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
09/22/2009US7592838 Method for communicating data and clock signals and corresponding signal, transmitter and receiver
09/22/2009US7592837 Low leakage and data retention circuitry
09/22/2009US7592836 Multi-write memory circuit with multiple data inputs
09/22/2009US7592834 Logic block control architectures for programmable logic devices
09/22/2009US7592833 Systems and methods involving field programmable gate arrays
09/22/2009US7592832 Adjustable transistor body bias circuitry
09/22/2009US7592831 Circuit to optimize charging of bootstrap capacitor with bootstrap diode emulator
09/22/2009US7592829 On-chip storage of secret information as inverse pair
09/22/2009CA2519977C Wear assembly for the digging edge of an excavator
09/22/2009CA2458060C Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
09/17/2009WO2008131142A3 System level interconnect with programmable switching
09/17/2009US20090235241 Flexible instruction processor systems and methods
09/17/2009US20090230995 Semiconductor device
09/17/2009US20090230994 Domino logic circuit and pipelined domino logic circuit
09/17/2009US20090230993 Low power high-speed output driver
09/17/2009US20090230992 Data transmission circuit capable of reducing current consumption
09/17/2009US20090230991 Level shifter circuit
09/17/2009US20090230990 Hardware and software programmable fuses for memory repair
09/17/2009US20090230989 Memory control circuit, memory control method, and integrated circuit
09/17/2009US20090230988 Electronic device having logic circuitry and method for designing logic circuitry
09/16/2009EP1776760B1 Energy recovery boost logic
09/16/2009EP1754163B1 Bus controller
09/16/2009CN201312302Y Thick film nine-path drive
09/16/2009CN101536313A Read-leveling implementations for ddr3 applications on an fpga
09/16/2009CN101534118A Controlled equivalent resistance module
09/16/2009CN101534117A A signal switching circuit
09/16/2009CN101534116A Data transmission circuit capable of reducing current consumption
09/16/2009CN101534115A Stepped capacitor array for a full binary weight capacitor
09/16/2009CN101534098A Integrator of lower-gain switch capacitance with non-sensitive parasitic effect and lower power consumption
09/16/2009CN101534097A Inverse integrator of lower-gain switch capacitance with non-sensitive parasitic effect and lower power consumption
09/16/2009CN101534051A A supply unit capable of fast switching output voltage
09/16/2009CN101533616A Multiplex driving circuit for liquid crystal display (LCD)
09/16/2009CN101533387A Parallel LU decomposition for corner sparse matrix based on FPGA
09/16/2009CN100542035C Output driver circuit
09/16/2009CN100541800C Buffer circuit having electrostatic discharge protection
09/16/2009CN100541458C Input/output interface of an integrated circuit device
09/15/2009US7589566 Semiconductor device provided with antenna ratio countermeasure circuit
09/15/2009US7589565 Low-power multi-output local clock buffer
09/15/2009US7589564 Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode
09/15/2009US7589562 I/O cell capable of finely controlling drive strength
09/15/2009US7589561 Tolerant CMOS receiver
09/15/2009US7589560 Apparatus for configuring I/O signal levels of interfacing logic circuits
09/15/2009US7589559 Current mode circuitry to modulate a common mode voltage
09/15/2009US7589558 Method and apparatus for configuring an integrated circuit
09/15/2009US7589557 Reversible input/output delay line for bidirectional input/output blocks
09/15/2009US7589555 Variable sized soft memory macros in structured cell arrays, and related methods
09/15/2009US7589554 I/O interface circuit of intergrated circuit
09/15/2009US7589553 Electronic module with organic logic circuit elements
1 ... 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 ... 420