Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
01/2010
01/27/2010EP2148443A1 Connection device for integrated circuit
01/27/2010CN201393217Y Circuit for preventing lock losing of high and low work frequency ends of phase lock loop
01/27/2010CN201393210Y Restoring circuit and impulse generation circuit thereof
01/27/2010CN101636909A Device for transforming input signals in output signals with different voltage ranges
01/27/2010CN101635568A Full swing amplitude current mode logic latch
01/27/2010CN101635567A Pulse driver with variable level displacement and variable output amplitude
01/27/2010CN100586022C Phase reverse, or/no gate, and/no gate with adjustable overturn point
01/27/2010CN100586021C Buffer circuit and integrated circuit
01/27/2010CN100586013C Delay circuit and semiconductor device including same
01/27/2010CN100585836C Semiconductor integrated circuit
01/27/2010CN100585741C Drive system and method for moving domain wall of ferromagnetic conduit
01/26/2010US7652507 Circuits and methods for detecting and assisting wire transitions
01/26/2010US7652506 Complementary signal generating circuit
01/26/2010US7652505 Level conversion circuit for converting voltage amplitude of signal
01/26/2010US7652504 Low latency, power-down safe level shifter
01/26/2010US7652503 Semiconductor device
01/26/2010US7652502 Field programmable gate arrays using resistivity sensitive memories
01/26/2010US7652500 Reconfiguration of programmable logic devices
01/26/2010US7652499 Embedding memory within tile arrangement of an integrated circuit
01/26/2010US7652498 Integrated circuit with delay selecting input selection circuitry
01/26/2010US7652398 Magnetic logic device
01/21/2010WO2010009142A1 Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks
01/21/2010WO2010008971A2 Apparatus and method for input/output module that optimizes frequency performance in a circuit
01/21/2010WO2010007654A1 Signal output circuit, timing generation circuit, testing device, and receiving circuit
01/21/2010WO2009145441A3 Inverter circuit
01/21/2010US20100014376 Decoding circuit withstanding high voltage via low-voltage mos transistor and the implementing method thereof
01/21/2010US20100014357 Flash-based fpga with secure reprogramming
01/21/2010US20100013519 Inverter circuit
01/21/2010US20100013518 Configuration backup device for the terminals of an integrated circuit and method of enabling the device
01/21/2010US20100013517 Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics
01/21/2010DE102004061326B4 Integrierte Schaltung Integrated circuit
01/20/2010EP2146434A1 A programmable logic device
01/20/2010EP2146433A2 Device for backing up the configuration of terminals of an integrated circuit, and method of implementing the device
01/20/2010EP2146432A1 Device for backing up the configuration of terminals of an integrated circuit, and method of implementing the device
01/20/2010EP2145389A1 Software programmable logic using spin transfer torque magnetoresistive devices
01/20/2010EP2145388A1 Five volt tolerant integrated circuit signal pad with three volt assist
01/20/2010EP2087592B1 Logic output stage of integrated circuit protected against battery inversion
01/20/2010EP1989780B1 Integrated circuit
01/20/2010CN201388188Y Time-ordered sequential control circuit and television having same
01/20/2010CN101632227A Electrical device for performing logic functions
01/20/2010CN101632226A Integrated circuit
01/20/2010CN101630956A NMOS power switch pipe drive circuit adopting starting strap circuit
01/20/2010CN101630955A High-performance level switch circuit with accelerating tube
01/20/2010CN101630954A Current driving circuit
01/20/2010CN100583850C Transmitter circuit, receiver circuit, interface circuit, and electronic device
01/20/2010CN100583638C Semiconductor device employing dynamic circuit
01/20/2010CN100583637C Pull-up circuit
01/20/2010CN100583636C Fan out buffer and method therefor
01/20/2010CN100583631C Transition detection at input of integrated circuit device
01/20/2010CN100583611C Method of switching a power supply of voltage domains of a semiconductor circuit, and corresponding semiconductor circuit
01/20/2010CN100583216C Semiconductor integrated circuit and liquid crystal display system
01/20/2010CN100583200C Display apparatus and portable telephone device
01/19/2010US7649990 Apparatus to implement dual hash algorithm
01/19/2010US7649770 Programming matrix
01/19/2010US7649386 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
01/19/2010US7649385 Logic with state retentive sleep mode
01/19/2010US7649384 High-voltage tolerant output driver
01/19/2010US7649383 Bidirectional level shift circuit and bidirectional bus system
01/19/2010US7649382 Apparatus to reduce voltage swing for control signals
01/19/2010US7649381 Level conversion circuit
01/19/2010US7649380 Logic circuits with electric field relaxation transistors and semiconductor devices having the same
01/19/2010US7649379 Reducing mission signal output delay in IC having mission and test modes
01/19/2010US7649130 Integrated circuit
01/14/2010WO2010004140A2 Programmable logic array, interconnection switch and logic unit for such an array
01/14/2010US20100008155 Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems
01/14/2010US20100007382 Inverter circuit and balanced input inverter circuit
01/14/2010US20100007381 Drive signal output circuit and multi-chip package
01/14/2010US20100007380 Level shifter and level shifting method thereof
01/14/2010US20100007379 Programmable logic devices with function-specific blocks
01/14/2010US20100007378 Programmable gate array, switch box and logic unit for such an array
01/14/2010US20100007377 Method and system for a serial peripheral interface
01/14/2010US20100007376 Storage elements for a configurable ic and method and apparatus for accessing data stored in the storage elements
01/14/2010US20100007373 Impedance matching logic
01/14/2010US20100007372 Semiconductor device
01/14/2010US20100007371 Testable tristate bus keeper
01/14/2010US20100007368 Semiconductor integrated circuit and method of testing the same
01/13/2010EP2143206A2 Electronic device with a high voltage tolerant unit
01/13/2010CN201382008Y Wind-speed gear control circuit of blast blower
01/13/2010CN101627541A Configurable circuit and configuration method
01/13/2010CN101626234A Resistive superconductive asynchronous bilinear logic AND gate circuit
01/13/2010CN101626233A Resistive superconductive asynchronous bilinear logic universal gate circuit
01/13/2010CN101626232A High speed phase splitting circuit
01/13/2010CN101626231A AISG tower mounted amplifier RET terminal RS485 circuit
01/13/2010CN101626230A Kline-RS232 circuit with function of preventing reverse connection
01/13/2010CN101626229A Circuit with calibration circuit portion
01/13/2010CN100581062C Decoding circuit with hierarchical structure
01/13/2010CN100581061C Tri-state buffer prepared from low voltage complementary metal oxide semiconductor
01/13/2010CN100581060C Circuit for generating synchronous delayed signals with short time and frequency multiplying circuit using the same
01/13/2010CN100580814C 移位寄存器 The shift register
01/13/2010CN100580761C LCD and residual shadow attenuation method
01/13/2010CN100580752C Drive circuit
01/13/2010CN100580650C Interface circuit and semiconductor integrated circuit
01/13/2010CN100580621C Data processing device, control method, automatic control device, terminal and generation method
01/13/2010CN100580620C Heat insulation 4-2 compressor and 4x4 multiplier based on CTGAL
01/12/2010US7646381 Integrated circuit device mountable on both sides of a substrate and electronic apparatus
01/12/2010US7646220 Reduced voltage subLVDS receiver
01/12/2010US7646219 Translator circuit having internal positive feedback
01/12/2010US7646218 Architecture and interconnect scheme for programmable logic circuits
01/12/2010US7646216 Low power mode
01/12/2010US7646215 Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus