| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 01/12/2010 | US7646214 Power harvesting signal line termination |
| 01/12/2010 | US7646213 On-die system and method for controlling termination impedance of memory device data bus terminals |
| 01/12/2010 | US7646212 Memory system including a power divider on a multi module memory bus |
| 01/12/2010 | US7646210 Method and system for low-power level-sensitive scan design latch with power-gated logic |
| 01/12/2010 | US7646209 Semiconductor integrated circuit and method of production of same |
| 01/07/2010 | WO2010001833A1 Memory/logic conjugate system |
| 01/07/2010 | WO2010001536A1 Semiconductor integrated circuit device |
| 01/07/2010 | US20100002512 Disabling faulty flash memory dies |
| 01/07/2010 | US20100001762 Domain crossing circuit and method |
| 01/07/2010 | US20100001761 Multi-function input terminal of integrated circuits |
| 01/07/2010 | US20100001760 Programmable system on a chip for power-supply voltage and current monitoring and control |
| 01/07/2010 | US20100001759 Configurable ic having a routing fabric with storage elements |
| 01/07/2010 | US20100001758 Controlling for variable impedance and voltage in a memory system |
| 01/07/2010 | US20100001757 Integrated circuit and method of protecting a circuit part to be protected of an integrated circuit |
| 01/06/2010 | EP2141812A1 Relaying circuit, information processing device, and relaying method |
| 01/06/2010 | EP2140548A2 Configurable ic having a routing fabric with storage elements |
| 01/06/2010 | CN101622787A Integrated circuit fuse array |
| 01/06/2010 | CN101621295A Three-value clock control heat insulation logic circuit of double-power clock |
| 01/06/2010 | CN101621294A Control logical circuit and successive approximation analog-to-digital converter |
| 01/06/2010 | CN101621293A JTAG device and method for realizing JTAG data downloading through isolating circuit |
| 01/06/2010 | CN101621292A Switch-capacitor integrator |
| 01/06/2010 | CN101620825A 半导体装置 Semiconductor device |
| 01/06/2010 | CN100578938C 电平移位电路 Level shift circuit |
| 01/05/2010 | US7644386 Redundancy structures and methods in a programmable logic device |
| 01/05/2010 | US7643632 Ternary and multi-value digital signal scramblers, descramblers and sequence generators |
| 01/05/2010 | US7642813 Error correcting logic system |
| 01/05/2010 | US7642811 Slew rate controlled output driver for use in semiconductor device |
| 01/05/2010 | US7642810 Input circuit for semiconductor integrated circuit |
| 01/05/2010 | US7642809 Die apparatus having configurable input/output and control method thereof |
| 01/05/2010 | US7642808 Impedance adjusting circuit and semiconductor memory device having the same |
| 12/31/2009 | US20090323830 Current mode circuitry to modulate a common mode voltage |
| 12/31/2009 | US20090322716 Semiconductor Device |
| 12/31/2009 | US20090322402 Semiconductor integrated circuit device |
| 12/31/2009 | US20090322382 Semiconductor Device, Driving Method Thereof and Electronic Device |
| 12/31/2009 | US20090322378 Electrical Device For Performing Logic Functions |
| 12/31/2009 | US20090322376 Smi memory read data capture margin characterization circuits and methods |
| 12/31/2009 | US20090322375 Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device |
| 12/31/2009 | US20090322374 Method and apparatus for controlling qubits with singel flux quantum logic |
| 12/30/2009 | WO2009157134A1 Semiconductor integrated circuit and i/o drive capacity adjustment method |
| 12/30/2009 | WO2009157126A1 Testing apparatus and driver circuit |
| 12/30/2009 | WO2008131138A3 Universal digital block with integrated arithmetic logic unit |
| 12/30/2009 | EP2137914A1 Lin receiver |
| 12/30/2009 | EP2137819A1 Device for transforming input signals in output signals with different voltage ranges |
| 12/30/2009 | EP2137818A1 Circuit device and method of controlling a voltage swing |
| 12/30/2009 | CN101615904A Data buffer and method for driving liquid crystal display device using same |
| 12/30/2009 | CN101615903A Method and circuit for configuring pin status |
| 12/30/2009 | CN100576746C Field programmable logical array wiring resource structure and its modeling approach thereof |
| 12/30/2009 | CN100576745C TTL and CMOS compatible input buffer |
| 12/30/2009 | CN100576739C Reconfigurable analog cell and arrangement comprising plurality of such cell |
| 12/30/2009 | CN100576536C Self-reparable semiconductor and system thereof |
| 12/30/2009 | CN100576355C Electronic circuit with array of programmable logic cells |
| 12/30/2009 | CN100576130C Power management system |
| 12/29/2009 | US7640528 Hardware acceleration of functional factoring |
| 12/29/2009 | US7639068 Voltage supply with low power and leakage current |
| 12/29/2009 | US7639047 Techniques for reducing clock skew in clock routing networks |
| 12/29/2009 | US7639046 Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit |
| 12/29/2009 | US7639045 Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback |
| 12/29/2009 | US7639043 LVDS receiver circuit |
| 12/29/2009 | US7639042 Methods of reducing power in programmable logic devices using low voltage swing for routing signals |
| 12/29/2009 | US7639041 Hotsocket-compatible body bias circuitry with power-up current reduction capabilities |
| 12/29/2009 | US7639040 Assembly with a mechanically inaccessible or difficult-to-access circuit and method for switching the operating state of an assembly |
| 12/29/2009 | US7639039 Semiconductor integrated circuit having current leakage reduction scheme |
| 12/29/2009 | US7639038 Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device |
| 12/29/2009 | US7639037 Method and system for sizing flow control buffers |
| 12/29/2009 | US7639036 Semiconductor integrated circuit |
| 12/29/2009 | US7639035 Qubit state copying |
| 12/29/2009 | US7638922 Method for ultra-fast controlling of a magnetic cell and related devices |
| 12/24/2009 | US20090316506 Serially Decoded Digital Device Testing |
| 12/24/2009 | US20090315590 Logic circuits, inverter devices and methods of operating the same |
| 12/24/2009 | US20090315589 Adjusting method and circuit using the same |
| 12/24/2009 | US20090315588 Variable sized soft memory macros in structured cell arrays, and related methods |
| 12/24/2009 | US20090315587 Key Based Pin Sharing Selection |
| 12/24/2009 | US20090315586 Setting Operating Mode of an Interface Using Multiple Protocols |
| 12/24/2009 | US20090315532 Very low power analog compensation circuit |
| 12/23/2009 | WO2009155370A1 Multi-level domino, bundled data, and mixed templates |
| 12/23/2009 | WO2009153921A1 Analog switch |
| 12/23/2009 | WO2009127848A3 Clock distribution buffer |
| 12/23/2009 | WO2009087450A9 System and method for reducing eme emissions in digital desynchronized circuits |
| 12/23/2009 | EP2136471A2 Logic circuits, inverter devices and methods of operating the same |
| 12/23/2009 | CN101609513A Semiconductor device and driving method thereof |
| 12/23/2009 | CN100574106C Multiplexing of digital signals at multiple supply voltages in integrated circuit |
| 12/23/2009 | CN100574105C Input circuits and methods thereof |
| 12/23/2009 | CN100574099C Oscillator and design method thereof |
| 12/23/2009 | CN100573646C Reference voltage generating circuit and liquid crystal display device using the same |
| 12/22/2009 | US7636006 Voltage supply interface circuit |
| 12/22/2009 | US7635990 Methods and apparatus for implementing an output circuit |
| 12/22/2009 | US7635989 Integrated circuits with bus-based programmable interconnect structures |
| 12/22/2009 | US7635988 Multi-port thin-film memory devices |
| 12/22/2009 | US7635987 Configuring circuitry in a parallel processing environment |
| 12/22/2009 | CA2442286C Wireless programmable logic devices |
| 12/22/2009 | CA2333623C Multiple-valued logic circuit architecture: supplementary symmetrical logic circuit structure (sus-loc) |
| 12/17/2009 | US20090309820 Gate driver and display panel utilizing the same |
| 12/17/2009 | US20090309631 Circuit with enhanced mode and normal mode |
| 12/17/2009 | US20090309630 Ternary valve input circuit |
| 12/17/2009 | US20090309627 Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits |
| 12/16/2009 | EP2133917A2 Semiconductor integrated circuit comprising mutli-threshold CMOS (MTCMOS) and non-MTCMOS circuit cells in the same circuit block |
| 12/16/2009 | EP2132874A1 Method and device for programming anti-fuses |
| 12/16/2009 | EP2132873A2 Level shifter circuit incorporating transistor snap-back protection |
| 12/16/2009 | EP1697924B1 Method for ultra-fast controlling of a magnetic cell and related devices |
| 12/16/2009 | CN201365236Y Complementary commutation drive circuit |