Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2009
03/26/2009US20090080465 Multiplexer circuit
03/26/2009US20090080260 Programmable CSONOS logic element
03/26/2009US20090079715 Gate driver and method of driving display apparatus having the same
03/26/2009US20090079483 Delay circuits matching delays of synchronous circuits
03/26/2009US20090079469 Semiconductor integrated circuit
03/26/2009US20090079468 Debug Network for a Configurable IC
03/26/2009US20090079467 Method and apparatus for upgrading fpga/cpld flash devices
03/26/2009US20090079466 Soft-reconfigurable massively parallel architecture and programming system
03/25/2009EP2040381A1 Semiconductor integrated circuit and layout technique thereof
03/25/2009EP2039007A2 Successive approximation analog to digital converter
03/25/2009EP2039005A2 Circuit configurations having four terminal jfet devices
03/25/2009EP2039003A2 Versatile and compact dc-coupled cml buffer
03/25/2009EP2038750A2 Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
03/25/2009EP2038727A2 Circuit and method for power management
03/25/2009EP1303913B1 Architecture and method for partially reconfiguring an fpga
03/25/2009CN101395801A Three-valued logic function circuit
03/25/2009CN101395800A Circuit arrangement and corresponding method for controlling and/or for preventing injection current
03/25/2009CN101394377A Pre-loading device and low voltage differential signal transmitter
03/25/2009CN101394177A Output buffer circuit
03/25/2009CN101393909A Serial transistor device and inverter circuit
03/25/2009CN100472956C Voltage generation circuit
03/25/2009CN100472429C Fast increment device of using zero detection and its increasing method
03/25/2009CN100472384C Power circuit
03/24/2009US7509613 Design method and architecture for power gate switch placement and interconnection using tapless libraries
03/24/2009US7509553 Inter-network and inter-protocol video conference privacy method, apparatus, and computer program product
03/24/2009US7509547 System and method for testing of interconnects in a programmable logic device
03/24/2009US7509192 In-vehicle mount type AV system and program
03/24/2009US7508251 Semiconductor integrated circuit apparatus
03/24/2009US7508247 Source drive circuit
03/24/2009US7508246 Performance variation compensating circuit and method
03/24/2009US7508237 Mainboard, electronic component, and controlling method of logic operation
03/24/2009US7508236 Line driver device
03/24/2009US7508235 Differential line termination technique
03/24/2009US7508234 Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array
03/24/2009US7508233 Full-adder of complementary carry logic voltage compensation
03/24/2009US7508231 Programmable logic device having redundancy with logic element granularity
03/24/2009US7508230 Digital programmable phase generator
03/19/2009WO2009033630A1 Logic chip, logic system and method for designing a logic chip
03/19/2009WO2009018285A3 Voltage tolerant floating n-well circuit
03/19/2009US20090077517 Semiconductor intergrated device and apparatus for designing the same
03/19/2009US20090077516 Semiconductor integrated device and apparatus for designing the same
03/19/2009US20090072888 Semiconductor integrated circuit
03/19/2009US20090072864 Output circuit
03/19/2009US20090072863 Transmission Gate Multiplexer
03/19/2009US20090072862 Semiconductor Device and Display Device
03/19/2009US20090072861 Wireline transmission circuit
03/19/2009US20090072860 Off-chip driver apparatus, systems, and methods
03/19/2009US20090072859 High speed io buffer
03/19/2009US20090072858 Heterogeneous configurable integrated circuit
03/19/2009US20090072857 Integrated circuits with adjustable body bias and power supply circuitry
03/19/2009US20090072856 Memory controller for heterogeneous configurable integrated circuits
03/18/2009CN101388664A Output circuit
03/18/2009CN101388663A Level shift circuit
03/18/2009CN101388662A Level shifting circuit
03/18/2009CN101388658A Mtcmos flip-flop with retention function
03/18/2009CN101388651A Receiver of high speed digital interface
03/18/2009CN101388185A Source driver and voltage drop detector thereof
03/18/2009CN100471064C Method and apparatus for generating non-skewed complementary signals through interpolation
03/18/2009CN100471053C Differential circuit and receiver with same
03/18/2009CN100470765C Adaptive threshold voltage control with positive body bias for N and P-channel transistors
03/18/2009CN100470629C Shift resistor circuit and method of operating the same
03/17/2009US7506227 Integrated circuit with embedded identification code
03/17/2009US7506199 Method and apparatus for recording and reproducing information
03/17/2009US7506146 Fast and compact circuit for bus inversion
03/17/2009US7505304 Fault tolerant asynchronous circuits
03/17/2009US7505053 Subpixel layouts and arrangements for high brightness displays
03/17/2009US7504872 Generic flexible timer design
03/17/2009US7504864 Method for controlling the evaluation time of a state machine
03/17/2009US7504863 Half-duplex communication system, low-voltage differential signaling transceiver of the system and pre-driver of the transceiver
03/17/2009US7504862 Level shifter translator
03/17/2009US7504861 Input stage for mixed-voltage-tolerant buffer with reduced leakage
03/17/2009US7504860 Voltage level shifting
03/17/2009US7504859 Level converter and semiconductor device
03/17/2009US7504858 Configurable integrated circuit with parallel non-neighboring offset connections
03/17/2009US7504857 Functional cells for automated I/O timing characterization of an integrated circuit
03/17/2009US7504856 Programming semiconductor dies for pin map compatibility
03/17/2009US7504855 Multiple data rate memory interface architecture
03/17/2009US7504854 Regulating unused/inactive resources in programmable logic devices for static power reduction
03/17/2009US7504853 Arrangement for compensation of ground offset in a data bus system
03/17/2009US7504852 Line reflection reduction with energy-recovery driver
03/17/2009US7504851 Fault tolerant asynchronous circuits
03/17/2009US7504850 Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit
03/12/2009WO2009033184A2 Clock guided logic with reduced switching
03/12/2009WO2009030997A2 Hardening of self-timed circuits against glitches
03/12/2009WO2009013422A3 Reconfigurable logic cell made up of double-gate mosfet transistors
03/12/2009US20090067632 Circuit updating system
03/12/2009US20090066429 Voltage detection circuit and oscillator using the same
03/12/2009US20090066374 Drive circuit, light emitting diode head, and image forming apparatus
03/12/2009US20090066369 Clock guided logic with reduced switching
03/12/2009US20090066368 Digital calibration circuits, devices and systems including same, and methods of operation
03/12/2009US20090066367 Input output device for mixed-voltage tolerant
03/12/2009US20090066366 Reprogrammable three dimensional intelligent system on a chip
03/12/2009US20090066365 Reprogrammable three dimensional field programmable gate arrays
03/12/2009US20090066364 Nonvolatile programmable logic circuit
03/12/2009US20090066362 Semiconductor integrated circuit
03/12/2009US20090066361 Semiconductor integrated circuit device and storage apparatus having the same
03/11/2009EP2033316A2 Fault tolerant integrated circuit architecture
03/11/2009EP2033315A2 Element controller for a resilient integrated circuit architecture
03/11/2009EP2033048A2 Optical logic devices having polarization based logic level representation and method of designing the same
03/11/2009EP1964266B1 A method for multi-cycle clock gating
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