Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
03/2010
03/09/2010US7675326 Dynamically-adjustable differential output drivers
03/09/2010US7675325 GTL backplane bus with improved reliability
03/09/2010US7675324 Pre-driver logic
03/09/2010US7675323 Differential signal receiver
03/09/2010US7675322 Level shifting circuits for generating output signals having similar duty cycle ratios
03/09/2010US7675320 Non-volatile memory architecture for programmable-logic-based system on a chip
03/09/2010US7675319 Programmable logic device having complex logic blocks with improved logic cell functionality
03/09/2010US7675318 Configuration setting circuit and configuration setting method thereof
03/09/2010US7675317 Integrated circuits with adjustable body bias and power supply circuitry
03/09/2010US7675315 Output stage with low output impedance and operating from a low power supply
03/09/2010US7675314 Receiver circuit
03/09/2010US7675313 Methods and systems for storing a security key using programmable fuses
03/04/2010WO2010024523A2 Transmitter and receiver of differential current driving mode, and interface system of differential current driving mode including the same
03/04/2010WO2010024126A1 Magnetoresistive element, logic gate, logical gate operation method
03/04/2010US20100058274 Flexible hardware upgrade mechanism for data communications equipment
03/04/2010US20100057389 Evaluating apparatus, a recording medium storing an evaluating program, and method for designing signal transmission system
03/04/2010US20100052775 Voltage supply with low power and leakage current
03/04/2010US20100052774 Circuit arrangement for controlling a high side cmos transistor in a high voltage deep sub micron process
03/04/2010US20100052729 Digital data inversion flag generator circuit
03/04/2010US20100052728 Load sense and active noise reduction for i/o circuit
03/04/2010DE102005034345B4 Verfahren und Schaltungen zur Datenverarbeitung auf Basis trinärer und quartärer Logik Methods and circuits for data processing based on trinary and quaternary logic
03/03/2010EP2159928A1 Apparatus and method for desiging signal transmission system
03/03/2010CN201418039Y AC dump sampling circuit
03/03/2010CN201417956Y Two-way transmission interface circuit between two different power sources for changing rise time
03/03/2010CN201417384Y Load running regulation and control device
03/03/2010CN101663816A Software programmable logic using spin transfer torque magnetoresistive devices
03/03/2010CN101662279A Level converting device
03/03/2010CN101662278A Three-order switchable constant Lyapunov exponent spectra chaotic circuit and using method thereof
03/03/2010CN101662277A Adaptive voltage bias control system and integrated circuit
03/03/2010CN101662276A Integrated circuit and its power management method
03/02/2010US7673274 Datapipe interpolation device
03/02/2010US7673201 Recovering a prior state of a circuit design within a programmable integrated circuit
03/02/2010US7672380 Noise-tolerant signaling schemes supporting simplified timing and data recovery
03/02/2010US7671656 Level converting circuit
03/02/2010US7671633 Glitch free 2-way clock switch
03/02/2010US7671632 Transmission system and method
03/02/2010US7671631 Low voltage differential signal receiving device
03/02/2010US7671630 USB 2.0 HS voltage-mode transmitter with tuned termination resistance
03/02/2010US7671629 Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains
03/02/2010US7671628 Bus interface and method for conveying multi-level communication signals between a communication bus and a device coupled to a communication bus
03/02/2010US7671627 Superscale processor performance enhancement through reliable dynamic clock frequency tuning
03/02/2010US7671626 Versatile logic element and logic array block
03/02/2010US7671625 Omnibus logic element
03/02/2010US7671624 Method to reduce configuration solution using masked-ROM
03/02/2010US7671622 On-die-termination control circuit and method
02/2010
02/25/2010WO2009148814A3 Programmable switch circuit and method, method of manufacture, and devices and systems including the same
02/25/2010WO2009126930A3 Voltage level shifter
02/25/2010US20100045359 Calibration circuit
02/25/2010US20100045349 Programmable high-speed interface
02/25/2010US20100045344 Dual rail domino circuit, domino circuit, and logic circuit
02/25/2010US20100045343 Current Limited Voltage Supply
02/25/2010US20100045342 Level translator circuit
02/25/2010US20100045339 wireline transmission circuit
02/25/2010US20100045338 Semiconductor device and data processing system including the same
02/25/2010US20100045337 Methods, apparatuses, and products for a secure circuit
02/25/2010US20100045336 Method and Device for Programmable Power Supply with Configurable Restrictions
02/24/2010EP2157697A1 Configurable circuit and configuration method
02/24/2010EP2156559A1 Adjustable input receiver for low power high speed interface
02/24/2010EP2156555A1 Techniques for multi-wire encoding with an embedded clock
02/24/2010CN201414209Y Music fountain audio level converter
02/24/2010CN201414124Y Isolation RS485 communication speed-raising circuit for low-speed optical coupler
02/24/2010CN201413492Y Microcontroller reset circuit of XFP module
02/24/2010CN201413332Y Rotating speed signal sampling circuit of motorcycle engine
02/24/2010CN101656535A Process mapping method for programmable gate array of multi-mode logical unit
02/24/2010CN101656534A Output-stage circuit and operational amplifier
02/24/2010CN101656533A Data signal loading circuit, display panel driving circuit, and image display apparatus
02/24/2010CN101656532A Multi-path data deployment device
02/24/2010CN101656531A Multi-function input terminal of integrated circuits
02/24/2010CN100592722C Differential line driver with on-chip termination
02/24/2010CN100592721C Line driver
02/24/2010CN100592631C Triple redundant latch design with storage node recovery
02/23/2010US7669163 Partial configuration of a programmable gate array using a bus macro and coupling the third design
02/23/2010US7669102 JTAG to SPI PROM conduit
02/23/2010US7667518 Method and apparatus for robust mode selection with low power consumption
02/23/2010US7667499 MuGFET circuit for increasing output resistance
02/23/2010US7667498 Relatively low standby power
02/23/2010US7667497 Process variation tolerant circuit with voltage interpolation and variable latency
02/23/2010US7667494 Methods and apparatus for fast unbalanced pipeline architecture
02/23/2010US7667493 Data transmitter
02/23/2010US7667492 Input buffer
02/23/2010US7667491 Low voltage output buffer and method for buffering digital output data
02/23/2010US7667490 Voltage shifter circuit
02/23/2010US7667489 Power-on reset circuit for a voltage regulator having multiple power supply voltages
02/23/2010US7667487 Techniques for providing switchable decoupling capacitors for an integrated circuit
02/23/2010US7667486 Non-sequentially configurable IC
02/23/2010US7667485 Semiconductor integrated circuits with power reduction mechanism
02/23/2010US7667483 Circuit and method for controlling termination impedance
02/18/2010WO2010019881A1 Gate level reconfigurable magnetic logic
02/18/2010WO2010017977A2 Simultaneous bi-directional data transfer
02/18/2010WO2010017643A1 Method and device for generating short pulses
02/18/2010WO2009135133A3 Integrated circuit having programmable logic cells
02/18/2010US20100039140 Buffer circuit of semiconductor memory apparatus
02/18/2010US20100039139 Reconfigurable sequencer structure
02/18/2010US20100039138 Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same
02/18/2010US20100039137 Download sequencing techniques for circuit configuration data
02/18/2010US20100039136 Gate Level Reconfigurable Magnetic Logic
02/18/2010US20100039135 Semiconductor integrated circuit
02/17/2010EP2153360A1 Methods and apparatuses for designing multiplexers
02/17/2010EP1488523B1 Implementation of wide multiplexers in reconfigurable logic
02/17/2010EP1330041B1 A method and an apparatus for improving the carriers' output power of a broadband multi-carrier base-station
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