Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
07/2004
07/20/2004US6765249 Thin-film transistors formed on a flexible substrate
07/20/2004US6765247 Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
07/20/2004US6765244 III nitride film and a III nitride multilayer
07/20/2004US6765243 HBT having a controlled emitter window opening
07/20/2004US6765242 Npn double heterostructure bipolar transistor with ingaasn base region
07/20/2004US6765241 Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances
07/20/2004US6765239 Semiconductor device having junction-termination structure of resurf type
07/20/2004US6765231 Semiconductor device and its manufacturing method
07/20/2004US6765230 Provides electrical relay between pixel electrode and thin film transistor; storage capacitance; simple configuration
07/20/2004US6765229 Method for producing semiconductor device
07/20/2004US6765227 Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding
07/20/2004US6765222 Detection of motive force applied to transport box mounted on a fims system
07/20/2004US6765203 Pallet assembly for substrate inspection device and substrate inspection device
07/20/2004US6765175 Laser irradiation apparatus, laser irradiation method, and manufacturing method for a semiconductor device
07/20/2004US6764966 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
07/20/2004US6764963 Manufacturing method of semiconductor devices
07/20/2004US6764961 Method of forming a metal gate electrode
07/20/2004US6764950 Fabrication method for semiconductor integrated circuit device
07/20/2004US6764949 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
07/20/2004US6764948 Method of manufacturing a semiconductor device and the semiconductor device manufactured by the method
07/20/2004US6764937 Solder on a sloped surface
07/20/2004US6764930 Method and structure for modular, highly linear MOS capacitors using nitrogen implantation
07/20/2004US6764927 Chemical vapor deposition (CVD) method employing wetting pre-treatment
07/20/2004US6764926 Method for obtaining high quality InGaAsN semiconductor devices
07/20/2004US6764921 Semiconductor device and method for fabricating the same
07/20/2004US6764918 Structure and method of making a high performance semiconductor device having a narrow doping profile
07/20/2004US6764917 SOI device with different silicon thicknesses
07/20/2004US6764913 Method for controlling an emitter window opening in an HBT and related structure
07/20/2004US6764912 Passivation of nitride spacer
07/20/2004US6764911 Multiple etch method for fabricating spacer layers
07/20/2004US6764910 Structure of semiconductor device and method for manufacturing the same
07/20/2004US6764909 Structure and method of MOS transistor having increased substrate resistance
07/20/2004US6764908 Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents
07/20/2004US6764907 Method of fabricating self-aligned silicon carbide semiconductor devices
07/20/2004US6764906 Method for making trench mosfet having implanted drain-drift region
07/20/2004US6764905 Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
07/20/2004US6764904 Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings
07/20/2004US6764902 Method of manufacturing semiconductor device
07/20/2004US6764900 Method of fabricating an X-ray detector array element
07/20/2004US6764898 Implantation into high-K dielectric material after gate etch to facilitate removal
07/20/2004US6764892 Device and method of low voltage SCR protection for high voltage failsafe ESD applications
07/20/2004US6764891 Physically defined varactor in a CMOS process
07/20/2004US6764889 Methods of forming vertical mosfets having trench-based gate electrodes within deeper trench-based source electrodes
07/20/2004US6764887 Method of forming a thin film transistor on a transparent plate
07/20/2004US6764884 Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
07/20/2004US6764883 Amorphous and polycrystalline silicon nanolaminate
07/20/2004US6764871 Method for fabricating a nitride semiconductor device
07/20/2004US6764774 Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same
07/20/2004CA2167396C Silicon pixel electrode
07/15/2004WO2004059756A1 Functional molecular element and functional molecular device
07/15/2004WO2004059745A1 Magnetic switching device and magnetic memory
07/15/2004WO2004059744A1 Compound semiconductor epitaxial substrate and method for manufacturing same
07/15/2004WO2004059743A1 Compound semiconductor epitaxial substrate and method for manufacturing same
07/15/2004WO2004059742A1 High electron mobility epitaxial substrate
07/15/2004WO2004059738A1 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell
07/15/2004WO2004059737A1 Multi-level memory cell with lateral floating spacers
07/15/2004WO2004059734A1 Testable electrostatic discharge protection circuits
07/15/2004WO2004059731A1 Silicon on sapphire structure (devices) with buffer layer
07/15/2004WO2004059727A1 Methods of forming structure and spacer and related finfet
07/15/2004WO2004059717A1 Thin film transistor, method for producing a thin film transistor and electronic device having such a transistor
07/15/2004WO2004059697A2 Adaptive negative differential resistance device
07/15/2004WO2004059682A1 Low-temperature formation method for emitter tip including copper oxide nanowire or copper oxide nanowire or copper nanowire and display device or light source having emitter tip manufactured using the same
07/15/2004WO2004044984A3 Chip-scale schottky device
07/15/2004WO2004038764A3 Semiconductor device with quantum well and etch stop
07/15/2004WO2004003970A9 A semiconductor device and method of fabricating a semiconductor device
07/15/2004WO2003085742A8 Method for forming a modified semiconductor having a plurality of band gaps
07/15/2004WO2003043810A3 Nanocrystal structures
07/15/2004WO2003043038A3 Mems device having contact and standoff bumps and related methods
07/15/2004US20040137761 Method for fabricating semiconductor device
07/15/2004US20040137722 Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner
07/15/2004US20040137720 Semiconductor device and manufacturing method for the same
07/15/2004US20040137704 Method of manufacturing memory with nano dots
07/15/2004US20040137703 MOSFET threshold voltage tuning with metal gate stack control
07/15/2004US20040137690 Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors
07/15/2004US20040137689 Low-GIDL MOSFET structure and method for fabrication
07/15/2004US20040137688 Semiconductor device with tapered gate and process for fabricating the device
07/15/2004US20040137685 Gate material for semiconductor device fabrication
07/15/2004US20040137684 Semiconductor device processing
07/15/2004US20040137683 [method of fabricating multi-bit flash memory]
07/15/2004US20040137675 Methods of manufacturing MOSFETS in semiconductor devices
07/15/2004US20040137672 Triple layer hard mask for gate patterning to fabricate scaled cmos transistors
07/15/2004US20040137671 Method of crystallizing amorphous silicon for use in thin film transistor
07/15/2004US20040137670 Self-aligned mask formed utilizing differential oxidation rates of materials
07/15/2004US20040137669 Methods of fabricating semiconductor devices
07/15/2004US20040137666 Low voltage super junction mosfet simulation and experimentation
07/15/2004US20040137665 Method for producing a thyristor
07/15/2004US20040137146 Forming a thin film structure
07/15/2004US20040136866 Thin semiconductors ; dielectric substrate
07/15/2004US20040136240 Memory device having high work function gate and method of erasing same
07/15/2004US20040136239 Semiconductor integrated circuit device with erasable and programmable fuse memory
07/15/2004US20040136140 Voltage-controlled variable-capacitance device
07/15/2004US20040135951 Integrated displays using nanowire transistors
07/15/2004US20040135756 High-definition liquid crystal display including sub scan circuit which separately controls plural pixels connected to the same main scan wiring line and the same sub scan wiring line
07/15/2004US20040135620 HF-controlled SCR-type switch
07/15/2004US20040135520 Organic electroluminescent device and manufacturing method for the same
07/15/2004US20040135248 Semiconductor device
07/15/2004US20040135237 Semiconductor device and method of manufacturing the same
07/15/2004US20040135236 Thin film transistor, its manufacture method and display device
07/15/2004US20040135229 Semiconductor device and method of setting input pin capacity
07/15/2004US20040135228 Semiconductor element