Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2005
07/28/2005US20050164609 Reducing wafer defects from chemical mechanical polishing
07/28/2005US20050164608 Apparatus for optical inspection of wafers during processing
07/28/2005US20050164604 Apparatus for transporting for polishing wafers
07/28/2005US20050164592 Manufacturing method and structure of copper lines for a liquid crystal panel
07/28/2005US20050164523 Substrate treating method
07/28/2005US20050164522 Optical fluids, and systems and methods of making and using the same
07/28/2005US20050164521 Zr-Sn-Ti-O films
07/28/2005US20050164520 Method for manufacturing semiconductor device
07/28/2005US20050164519 Methods of forming planarized surfaces over semiconductor substrates
07/28/2005US20050164518 Oxidation method and oxidation system
07/28/2005US20050164517 In-situ-etch-assisted HDP deposition using SiF4
07/28/2005US20050164516 Method and structure for graded gate oxides on vertical and non-planar surfaces
07/28/2005US20050164514 Method for etching a quartz layer in a photoresistless semiconductor mask
07/28/2005US20050164513 Plasma etch reactor and method
07/28/2005US20050164512 Method of manufacturing semiconductor device
07/28/2005US20050164511 Method and system for etching a high-k dielectric material
07/28/2005US20050164510 Chemical mechanical polishing aqueous dispersion and chemical mechanical polishing method
07/28/2005US20050164509 Method of protecting semiconductor wafer and adhesive film for protection of semiconductor wafer
07/28/2005US20050164507 Negative photoresist composition including non-crosslinking chemistry
07/28/2005US20050164506 Method and apparatus for backside polymer reduction in dry-etch process
07/28/2005US20050164505 Land grid array membrane
07/28/2005US20050164504 Method for etching high aspect ratio features in III-V based compounds for optoelectronic devices
07/28/2005US20050164503 Method and structure for ultra narrow gate
07/28/2005US20050164502 Immersion liquids for immersion lithography
07/28/2005US20050164500 Selective passivation of exposed silicon
07/28/2005US20050164499 Electroless plating method and apparatus
07/28/2005US20050164498 Plating method and plating apparatus
07/28/2005US20050164497 Pretreatment for electroless deposition
07/28/2005US20050164496 Pretreatment for an electroplating process and an electroplating process in including the pretreatment
07/28/2005US20050164495 Method to improve planarity of electroplated copper
07/28/2005US20050164494 Method for forming semiconductor device
07/28/2005US20050164493 Shared contact for high-density memory cell design
07/28/2005US20050164491 Bit line contact hole and method for forming the same
07/28/2005US20050164490 Methods of forming backside connections on a wafer stack
07/28/2005US20050164489 Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
07/28/2005US20050164488 Method of fabricating a plurality of ferroelectric capacitors
07/28/2005US20050164487 Formation of a tantalum-nitride layer
07/28/2005US20050164486 Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same
07/28/2005US20050164485 Method for fabricating semiconductor device and apparatus for fabricating the same
07/28/2005US20050164483 Method of forming solder bump with reduced surface defects
07/28/2005US20050164482 Silicon Carbide on Diamond Substrates and Related Devices and Methods
07/28/2005US20050164481 Method and structure for reducing contact aspect ratios
07/28/2005US20050164480 Interface layer for the fabrication of electronic devices
07/28/2005US20050164479 Zirconium oxide and hafnium oxide etching using halogen containing chemicals
07/28/2005US20050164478 Novel method of trimming technology
07/28/2005US20050164477 Strained silicon on relaxed sige film with uniform misfit dislocation density
07/28/2005US20050164476 Method for production of deep p regions in silicon, and semiconductor components produced using the method
07/28/2005US20050164475 Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
07/28/2005US20050164474 Method for depositing high-quality microcrystalline semiconductor materials
07/28/2005US20050164473 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
07/28/2005US20050164472 Method for separating electronic components from a composite
07/28/2005US20050164471 Method for producing thin layers of semiconductor material from a donor wafer
07/28/2005US20050164470 Method for fabricating a semiconductor device by transferring a layer to a support with curvature
07/28/2005US20050164469 Method for N+ doping of amorphous silicon and polysilicon electrodes in deep trenches
07/28/2005US20050164468 Selective silicon-on-insulator isolation structure and method
07/28/2005US20050164467 Semiconductor device and a method of manufacturing the same
07/28/2005US20050164466 Methods for forming small-scale capacitor structures
07/28/2005US20050164464 Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition
07/28/2005US20050164463 Multi-stage EPI process for forming semiconductor devices, and resulting device
07/28/2005US20050164462 Semiconductor device and fabricating method thereof
07/28/2005US20050164461 Method for forming a junction region of a semiconductor device
07/28/2005US20050164460 Salicide process for metal gate CMOS devices
07/28/2005US20050164459 Soft-landing etching method using doping level control
07/28/2005US20050164458 Lightly doped drain MOS transistor
07/28/2005US20050164457 Non-volatile memory devices and methods of fabricating the same
07/28/2005US20050164456 Method for fabricating an NROM memory cell array
07/28/2005US20050164455 Method of manufacturing a semiconductor device
07/28/2005US20050164454 Selective epitaxy vertical integrated circuit components and methods
07/28/2005US20050164453 Method of manufacturing nonvolatile semiconductor storage device
07/28/2005US20050164452 Mirror image non-volatile memory cell transistor pairs with single poly layer
07/28/2005US20050164451 Twin insulator charge storage device operation and its fabrication method
07/28/2005US20050164450 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell
07/28/2005US20050164449 Microelectronic capacitor structure and method for fabrication thereof
07/28/2005US20050164448 Method for manufacturing a semiconductor device
07/28/2005US20050164447 Method and structure for vertical DRAM devices with self-aligned upper trench shaping
07/28/2005US20050164446 Method for manufacturing single-sided buried strap in semiconductor devices
07/28/2005US20050164445 System and method for integration of HfO2 and RTCVD poly-silicon
07/28/2005US20050164444 Selective nitridation of gate oxides
07/28/2005US20050164443 Tunable sidewall spacer process for CMOS integrated circuits
07/28/2005US20050164442 Method of manufacturing a nonvolatile semiconductor memory device
07/28/2005US20050164441 Semiconductor device and process for producing the same
07/28/2005US20050164440 Salicided MOS device and one-sided salicided MOS device, and simultaneous fabrication method thereof
07/28/2005US20050164439 Low volt/high volt transistor
07/28/2005US20050164438 Method for manufacturing a semiconductor device
07/28/2005US20050164437 Method of manufacturing semiconductor device
07/28/2005US20050164436 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
07/28/2005US20050164435 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
07/28/2005US20050164434 Method of fabricating semiconductor device
07/28/2005US20050164433 Ultra thin channel MOSFET
07/28/2005US20050164432 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
07/28/2005US20050164431 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
07/28/2005US20050164430 Semiconductor device having a fuse
07/28/2005US20050164429 Method for fabricating a chip scale package using wafer level processing
07/28/2005US20050164427 Non-volatile semiconductor memory device and method of manufacturing the same
07/28/2005US20050164426 Micro-mirror package
07/28/2005US20050164424 Silison film for thin film transistors
07/28/2005US20050164423 Display device, manufacturing method thereof, and television receiver
07/28/2005US20050164421 Pixel design to maximize photodiode capacitance and method of forming same
07/28/2005US20050164419 Group III Nitride Crystal Substrate, Method of Its Manufacture, and Group-III Nitride Semiconductor Device
07/28/2005US20050164418 Nitride semiconductor, semiconductor device, and method of manufacturing the same
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