Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2006
02/02/2006WO2005057280A3 Lithographic apparatus and device manufacturing method
02/02/2006WO2005055288A3 Method and device for the alternating contacting of two wafers
02/02/2006WO2005048301A3 Methods and apparatus for optimizing a substrate in a plasma processing system
02/02/2006WO2005045901A8 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
02/02/2006WO2005042160A3 Reaction system for growing a thin film
02/02/2006WO2005034187A3 Monitoring system comprising infrared thermopile detector
02/02/2006WO2005029180A3 Applications of semiconductor nano-sized particles for photolithography
02/02/2006WO2004095510A3 Multilayered cap barrier in microelectronic, interconnect structures
02/02/2006US20060025956 Semiconductor device fabrication method
02/02/2006US20060025948 Inspection system setup techniques
02/02/2006US20060025501 Semiconductor encapsulating epoxy resin Composition and semiconductor device
02/02/2006US20060025500 No-flow underfill composition and method
02/02/2006US20060025320 Seminconductor surface treatment and mixture used therein
02/02/2006US20060024989 Helical microelectronic contact and method for fabricating same
02/02/2006US20060024988 Interconnect assemblies and methods
02/02/2006US20060024981 Method of manufacturing semiconductor device
02/02/2006US20060024980 Silica-based film, method of forming the same, composition for forming insulating film for semiconductor device, interconnect structure, and semiconductor device
02/02/2006US20060024979 Fabrication method of semiconductor device
02/02/2006US20060024978 Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects
02/02/2006US20060024977 Low dielectric constant carbon films
02/02/2006US20060024976 Ultraviolet assisted porogen removal and/or curing processes for forming porous low k dielectrics
02/02/2006US20060024975 Atomic layer deposition of zirconium-doped tantalum oxide films
02/02/2006US20060024974 Surface treatment for oxidation removal in integrated circuit package assemblies
02/02/2006US20060024973 Methods of etching a contact opening over a node location on a semiconductor substrate
02/02/2006US20060024972 Silicon recess improvement through improved post implant resist removal and cleans
02/02/2006US20060024971 Dry etching method using polymer mask selectively formed by CO gas
02/02/2006US20060024970 Method for preparing a semiconductor substrate surface for semiconductor device fabrication
02/02/2006US20060024969 Method for purifying silicon carbide coated structures
02/02/2006US20060024968 Method for stripping photoresist from etched wafer
02/02/2006US20060024967 Polishing composition for noble metals
02/02/2006US20060024966 Manufacturing method of semiconductor device
02/02/2006US20060024965 Method of etching cavities having different aspect ratios
02/02/2006US20060024964 Method and apparatus of forming thin film using atomic layer deposition
02/02/2006US20060024963 Metal-germanium physical vapor deposition for semiconductor device defect reduction
02/02/2006US20060024962 Partial plate anneal plate process for deposition of conductive fill material
02/02/2006US20060024961 Interlevel dielectric layer and metal layer sealing
02/02/2006US20060024960 Method for producing thin semiconductor films by deposition from solution
02/02/2006US20060024959 Thin tungsten silicide layer deposition and gate metal integration
02/02/2006US20060024958 HSQ/SOG dry strip process
02/02/2006US20060024957 Methods for forming contact hole, for manufacturing circuit board and for manufacturing electro-optical device
02/02/2006US20060024956 Method of eliminating etch ridges in a dual damascene process
02/02/2006US20060024955 Nitrogen-free ARC/capping layer and method of manufacturing the same
02/02/2006US20060024954 Copper damascene barrier and capping layer
02/02/2006US20060024953 Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess
02/02/2006US20060024952 Method of producing semiconductor device
02/02/2006US20060024951 Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer
02/02/2006US20060024950 Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same
02/02/2006US20060024949 Method of manufacturing semiconductor device
02/02/2006US20060024948 Method of fabricating dual damascene interconnection
02/02/2006US20060024947 Electronic component comprising predominantly organic functional materials and a method for the production thereof
02/02/2006US20060024946 Method for filling a contact hole and integrated circuit arrangement with contact hole
02/02/2006US20060024945 Method for fabricating semiconductor device using amorphous carbon layer as sacrificial hard mask
02/02/2006US20060024944 Metal pad of semiconductor device and method for bonding the metal pad
02/02/2006US20060024943 Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present
02/02/2006US20060024942 Semiconductor constructions comprising multi-level patterns of radiation-imageable material; and methods of forming wire bonds for semiconductor constructions
02/02/2006US20060024941 Method of forming metal interconnect of semiconductor device
02/02/2006US20060024940 Borderless contact structures
02/02/2006US20060024939 Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers
02/02/2006US20060024938 Method for reducing metal silicide excessive encroachment defects in the manufacture of a semiconductor device having silicided source/drain regions
02/02/2006US20060024937 Methods for forming wiring and electrode
02/02/2006US20060024936 Nanostructured electrodes
02/02/2006US20060024935 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing
02/02/2006US20060024934 Chemical treatment to retard diffusion in a semiconductor overlayer
02/02/2006US20060024933 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
02/02/2006US20060024932 Methods of forming semiconductor devices including removing a thickness of a polysilicon gate layer
02/02/2006US20060024931 Dual SIMOX hybrid orientation technology (HOT) substrates
02/02/2006US20060024930 Method of implanting using a shadow effect
02/02/2006US20060024929 Method of forming a well in a substrate of a transistor of a semiconductor device
02/02/2006US20060024928 Methods for controlling dopant concentration and activation in semiconductor structures
02/02/2006US20060024927 Methods of forming a P-well in an integrated circuit device
02/02/2006US20060024926 Method of forming a controlled and uniform lightly phosphorous doped silicon film
02/02/2006US20060024925 Crystalline semiconductor film, method of manufacturing the same, and semiconductor device
02/02/2006US20060024924 Manufacturing method for semiconductor devices, and formation apparatus for semiconductor wafer dicing masks
02/02/2006US20060024923 Deep alignment marks on edge chips for subsequent alignment of opaque layers
02/02/2006US20060024922 Method for cutting wafer
02/02/2006US20060024921 [method of relieving wafer stress]
02/02/2006US20060024920 Method for positioning dicing line of wafer
02/02/2006US20060024919 Method and apparatus for micro-electro mechanical system package
02/02/2006US20060024918 Semiconductor memory device and manufacturing method of the same
02/02/2006US20060024917 Method and system for fabricating strained layers for the manufacture of integrated circuits
02/02/2006US20060024916 Modification of electrical properties for semiconductor wafers
02/02/2006US20060024915 Method for manufacturing soi wafer
02/02/2006US20060024914 Wet etching method of removing silicon from a substrate and method of forming trench isolation
02/02/2006US20060024913 Methods for manufacturing shallow trench isolation layers of semiconductor devices
02/02/2006US20060024912 Method for manufacturing device isolation film of semiconductor device
02/02/2006US20060024911 Method to design for or modulate the CMOS transistor inverse narrow width effect (INWE) using shallow trench isolation (STI)
02/02/2006US20060024910 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
02/02/2006US20060024909 Shallow trench isolation method
02/02/2006US20060024908 Method of reducing the surface roughness of a semiconductor wafer
02/02/2006US20060024907 Method of forming a capacitor
02/02/2006US20060024906 Semiconductor device and a method of manufacturing the same
02/02/2006US20060024905 Metal capacitor stacked with a MOS capacitor to provide increased capacitance density
02/02/2006US20060024904 Methods of forming a capacitors -
02/02/2006US20060024903 Methods of forming capacitors
02/02/2006US20060024902 Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect
02/02/2006US20060024901 Method for fabricating a high-frequency and high-power semiconductor module
02/02/2006US20060024900 Interposer including at least one passive element at least partially defined by a recess formed therein, method of manufacture, system including same, and wafer-scale interposer
02/02/2006US20060024899 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode
02/02/2006US20060024898 Increased drive current by isotropic recess etch
02/02/2006US20060024897 Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions