Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2011
03/31/2011WO2011036778A1 Pattern formation process
03/31/2011WO2011036775A1 Nonvolatile semiconductor memory
03/31/2011WO2011036770A1 Pass transistor circuit with memory function, and switching box circuit provided with pass transistor circuit
03/31/2011WO2011036753A1 Magnetic memory
03/31/2011WO2011036752A1 Resonant tunneling magnetoresistance effect element, magnetic memory cell, and magnetic random access memory
03/31/2011WO2011036496A1 Improved selectivity in a xenon difluoride etch process
03/31/2011WO2011036428A1 Ultra-low voltage coefficient capacitors
03/31/2011WO2011036250A1 Electro-optic component, use and production of said component
03/31/2011WO2011036214A1 A memory device and a method of manufacturing the memory device
03/31/2011WO2011036078A1 Modular substrate processing system and method
03/31/2011WO2011035848A2 Method for producing a solar cell or a transistor having a crystalline silicon thin-film layer
03/31/2011WO2011035748A1 Method and device for etching back a semiconductor layer
03/31/2011WO2011035727A1 Method for fabricating trench dmos transistor
03/31/2011WO2011016832A3 Electronic device including graphene-based layer(s),and/or method of making the same
03/31/2011WO2011011140A3 Method and materials for double patterning
03/31/2011WO2011008531A3 Enhancement mode hemt for digital and analog applications
03/31/2011WO2011008499A3 Leak proof pad for cmp endpoint detection
03/31/2011WO2011008478A3 System and method for performing photothermal measurements and relaxation compensation
03/31/2011WO2011008456A3 Methods of forming oxide layers on substrates
03/31/2011WO2011007967A3 Apparatus for manufacturing semiconductors
03/31/2011WO2011002778A3 Methods and structures for a vertical pillar interconnect
03/31/2011WO2010151857A3 Method for forming iii-v semiconductor structures including aluminum-silicon nitride passivation
03/31/2011WO2010151856A3 Chemical vapor deposition process for aluminum silicon nitride
03/31/2011WO2010148385A3 Thin film temperature measurement using optical absorption edge wavelength
03/31/2011WO2010148293A3 Euv high throughput inspection system for defect detection on patterned euv masks, mask blanks, and wafers
03/31/2011WO2010148266A3 Vertical junction field effect transistors and diodes having graded doped regions and methods of making
03/31/2011WO2010147356A3 Wafer processing base
03/31/2011WO2010143852A3 Wafer prober station in which the mechanical strength of a chuck is enhanced, and method for controlling same
03/31/2011WO2010140870A3 Method for forming fine pattern in semiconductor device
03/31/2011WO2010140788A3 Chemical-mechanical polishing slurry composition comprising nonionized heat-activated nanocatalyst, and polishing method using same
03/31/2011WO2010133989A3 Arrangements and methods for improving bevel etch repeatability among substrates
03/31/2011WO2010132640A3 Electrostatic chuck with polymer protrusions
03/31/2011WO2010132172A3 Method for tuning a deposition rate during an atomic layer deposition process
03/31/2011WO2010129431A3 Thermocouple and temperature measuring system
03/31/2011WO2010126902A4 Temperature control of chemical mechanical polishing
03/31/2011WO2010125011A3 Method for producing semiconductive layers
03/31/2011WO2010120765A3 Implant mask with moveable mask segments
03/31/2011WO2010120704A3 Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges
03/31/2011WO2010120128A3 Method for manufacturing a polishing retainer ring and retainer ring manufactured thereby
03/31/2011WO2010117626A3 Lithography modelling and applications
03/31/2011WO2010113089A3 Device for treating disc-like articles
03/31/2011US20110076858 Methods for Coating the Backside of Semiconductor Wafers
03/31/2011US20110076857 Method of manufacturing semiconductor device and substrate processing apparatus
03/31/2011US20110076856 Semiconductor die with protective layer and related method of processing a semiconductor wafer
03/31/2011US20110076855 Laminate and use thereof
03/31/2011US20110076854 Method of manufacturing vertical-cavity surface emitting laser
03/31/2011US20110076853 Novel process method for post plasma etch treatment
03/31/2011US20110076852 Cleaning composition, cleaning process, and process for producing semiconductor device
03/31/2011US20110076851 Method for fabricating fine pattern in semiconductor device
03/31/2011US20110076850 Method of fabricating semiconductor device
03/31/2011US20110076849 Process for bonding and transferring a layer
03/31/2011US20110076848 Semiconductor process chamber and seal
03/31/2011US20110076847 Laser system for processing solar wafers in a carrier
03/31/2011US20110076846 Semiconductor device having fine contacts and method of fabricating the same
03/31/2011US20110076845 Method Of Forming An Interconnect Of A Semiconductor Device
03/31/2011US20110076844 Superior fill conditions in a replacement gate approach by performing a polishing process based on a sacrificial fill material
03/31/2011US20110076843 Lithography patterning method
03/31/2011US20110076842 Method of fabricating semiconductor device
03/31/2011US20110076841 Forming catalyzed ii-vi semiconductor nanowires
03/31/2011US20110076840 Method of Manufacturing a Fast Recovery Rectifier
03/31/2011US20110076839 Making films composed of semiconductor nanocrystals
03/31/2011US20110076838 Gettering structures and methods and their application
03/31/2011US20110076837 Manufacturing method of soi substrate and manufacturing method of semiconductor device
03/31/2011US20110076836 Method for the ultrasonic planarization of a substrate, from one surface of which a buried weakened layer has been uncovered by fracture
03/31/2011US20110076835 Semiconductor device having an expanded storage node contact and method for fabricating the same
03/31/2011US20110076834 Semiconductor device and method for semiconductor device
03/31/2011US20110076833 Method of manufacturing semiconductor device
03/31/2011US20110076832 Dual etch method of defining active area in semiconductor device
03/31/2011US20110076831 Solving Via-Misalignment Issues in Interconnect Structures Having Air-Gaps
03/31/2011US20110076830 Method for manufacturing semiconductor substrate
03/31/2011US20110076829 Semiconductor Devices and Methods of Forming the Same
03/31/2011US20110076828 Method for manufacturing capacitor lower electrodes of semiconductor memory
03/31/2011US20110076827 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
03/31/2011US20110076826 Passivating glue layer to improve amorphous carbon to metal adhesion
03/31/2011US20110076825 Method for Making a Self Aligning Memory Device
03/31/2011US20110076824 Fabrication method of phase change random access memory device
03/31/2011US20110076823 Method for fabricating a semiconductor device
03/31/2011US20110076822 Lateral metal oxide semiconductor drain extension design
03/31/2011US20110076821 Semiconductor device and manufacturing method of the same
03/31/2011US20110076820 Semiconductor integrated circuit device and process for manufacturing the same
03/31/2011US20110076819 Three-dimensional semiconductor memory device and method of fabricating the same
03/31/2011US20110076818 Insulated gate type semiconductor device and method for fabricating the same
03/31/2011US20110076817 Integrated circuit device with a semiconductor body and method for the production of an integrated circuit device
03/31/2011US20110076816 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
03/31/2011US20110076815 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection
03/31/2011US20110076814 Method for fabricating strained-silicon cmos transistor
03/31/2011US20110076813 Semiconductor Device with both I/O and Core Components and Method of Fabricating Same
03/31/2011US20110076812 Semiconductor device and method of manufacturing the same
03/31/2011US20110076811 Method of Manufacturing a Semiconductor Device
03/31/2011US20110076810 Three Dimensional Multilayer Circuit
03/31/2011US20110076809 Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
03/31/2011US20110076808 Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers
03/31/2011US20110076807 Self locking and aligning clip structure for semiconductor die package
03/31/2011US20110076806 Low Cost Lead-Free Preplated Leadframe Having Improved Adhesion and Solderability
03/31/2011US20110076805 Molded leadframe substrate semiconductor package
03/31/2011US20110076804 Power device packages and methods of fabricating the same
03/31/2011US20110076803 Wafer-level stack package
03/31/2011US20110076802 Embedded chip package process
03/31/2011US20110076801 Method for manufacturing semiconductor device
03/31/2011US20110076800 Manufacturing method of semiconductor device