G11C - Static stores - Patents Sitemap

More topics under "G11C - Static stores" (278,845)
G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
G11C 13 - Digital stores characterised by the use of storage elements not covered by groups , , or (8,663)
G11C 14 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down (1,872)
G11C 15 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores (3,555)
G11C 16 - Erasable programmable read-only memories (44,373)
G11C 17 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards (10,133)
G11C 19 - Digital stores in which the information is moved stepwise, e.g. shift registers (6,160)
G11C 21 - Digital stores in which the information circulates (125)
G11C 23 - Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor (468)
G11C 25 - Digital stores characterised by the use of flowing media; Storage elements therefor (19)
G11C 27 - Electric analogue stores, e.g. for storing instantaneous values (3,965)
G11C 29 - Checking stores for correct operation; Testing stores during standby or offline operation (30,524)
G11C 5 - Details of stores covered by group (20,391)
G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
G11C 8 - Arrangements for selecting an address in a digital store (19,368)
G11C 99 - Subject matter not provided for in other groups of this subclass (24)

Patents for G11C - Static stores (462)
03/2005
03/17/2005	CA2537632A1 Low voltage operation dram control circuits
03/10/2005	WO2004112040A3 Methods of increasing the reliability of a flash memory
03/08/2005	US6864551 High density and high programming efficiency MRAM design
03/03/2005	WO2005020241A2 Fowler-nordheim block alterable eeprom memory cell
03/03/2005	WO2004095457A3 Initialization and update of software and/or firmware in electronic devices
03/03/2005	WO2004034401A3 Dynamic memory supporting simultaneous refresh and data-access transactions
02/2005
02/22/2005	US6858442 Ferroelectric memory integrated circuit with improved reliability
02/17/2005	US20050037571 Fowler-Nordheim block alterable EEPROM memory cell
02/17/2005	US20050036393 Scalable flash EEPROM memory cell with notched floating gate and graded source region, and method of manufacturing the same
02/10/2005	WO2005013281A2 Nonvolatile memory and method of making same
02/10/2005	WO2004097837A3 Method of dual cell memory device operation for improved end-of-life read margin
02/03/2005	US20050024928 Asynchronous static random access memory
01/2005
01/27/2005	WO2005008672A2 Asynchronous static random access memory
01/27/2005	US20050018474 SRAM cell structure and circuits
01/26/2005	CN1572002A Noise suppression for open bit line DRAM architectures
01/20/2005	WO2005006340A2 Sram cell structure and circuits
01/20/2005	WO2005006339A2 A scalable flash eeprom memory cell with notched floating gate and graded source region, and method of manufacturing the same
01/20/2005	WO2005006338A2 Magnetoelectronics information device having a compound magnetic free layer
01/20/2005	WO2005006337A2 Variable gate bias for a reference transistor in a non-volatile memory
01/20/2005	US20050015557 Nonvolatile memory unit with specific cache
01/20/2005	US20050014334 Method for making high density nonvolatile memory
01/20/2005	US20050014322 Method for making high density nonvolatile memory
01/20/2005	US20050013165 Flash memories with adaptive reference voltages
01/20/2005	US20050012220 Contacts for an improved high-density nonvolatile memory
01/20/2005	US20050012154 Method for making high density nonvolatile memory
01/20/2005	US20050012120 Method for making high density nonvolatile memory
01/20/2005	US20050012119 Method for making high density nonvolatile memory
01/20/2005	CA2529667A1 Sram cell structure and circuits
01/13/2005	WO2005004160A2 Method for updating software of an electronic control device by flash programming via a serial interface and corresponding automatic state machine
01/13/2005	US20050007820 Variable gate bias for a reference transistor in a non-volatile memory
01/06/2005	WO2005001840A2 Mirror image non-volatile memory cell transistor pairs with single poly layer
01/04/2005	US6839280 Variable gate bias for a reference transistor in a non-volatile memory
12/2004
12/29/2004	WO2004114312A2 Magnetic memory device on low-temperature substrate
12/23/2004	WO2004112040A2 Methods of increasing the reliability of a flash memory
12/23/2004	WO2004079744A3 Magnetic memory cell junction and method for forming a magnetic memory cell junction
12/23/2004	US20040257902 Magnetoresistive random access memory device structures and methods for fabricating the same
12/16/2004	US20040252559 Transplanted magnetic random access memory (MRAM) devices on thermally-sensitive substrates using laser transfer and method for making the same
11/2004
11/25/2004	WO2004102576A2 Semiconductor memory device and method of operating same
11/18/2004	WO2004100169A2 Mram architecture with a bit line located underneath the magnetic tunneling junction device
11/18/2004	US20040228168 Semiconductor memory device and method of operating same
11/18/2004	DE102004018473A1 Monolithische Lesen-beim-Schreiben-Flashspeicher-Vorrichtung Monolithic read-while-write flash memory device
11/11/2004	WO2004097837A2 Method of dual cell memory device operation for improved end-of-life read margin
11/11/2004	WO2004097835A2 Nonvolatile memory structure with high speed high bandwidth and low voltage
11/11/2004	US20040222450 MRAM architecture with a bit line located underneath the magnetic tunneling junction device
11/09/2004	US6816414 Nonvolatile memory and method of making same
11/04/2004	WO2004095460A2 Asynchronous jitter reduction technique
11/04/2004	WO2004095459A2 Magnetoresistive ram device and methods for fabricating
11/04/2004	WO2004095458A2 Method and apparatus for noise shaping in direct digital synthesis circuits
11/04/2004	WO2004095457A2 Initialization and update of software and/or firmware in electronic devices
11/04/2004	WO2004077438A3 Process of forming a ferroelectric memory integrated circuit
11/04/2004	WO2004072978A3 High density and high programming efficiency mram design
11/04/2004	CA2520139A1 Asynchronous jitter reduction technique
10/2004
10/28/2004	WO2004093084A2 Mram architecture and a method and system for fabricating mram memories utilizing the architecture
10/28/2004	US20040212004 Mirror image non-volatile memory cell transistor pairs with single poly layer
10/21/2004	US20040210709 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
10/21/2004	US20040210611 Method and apparatus for noise shaping in direct digital synthesis circuits
10/21/2004	US20040206981 Monolithic read-while-write flash memory device
10/13/2004	EP1104579B1 Memory supervision
10/07/2004	WO2004086406A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
10/07/2004	CA2520492A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
09/2004
09/30/2004	US20040191928 MRAM architecture and a method and system for fabricating MRAM memories utilizing the architecture
09/23/2004	WO2004066307A3 Stacked memory cell having diffusion barriers
09/16/2004	WO2004079744A2 Magnetic memory cell junction and method for forming a magnetic memory cell junction
09/16/2004	WO2004079742A2 Method of forming a flux concentrating layer of a magnetic device
09/16/2004	US20040178404 Multiple bit chalcogenide storage device
09/10/2004	WO2004077438A2 Process of forming a ferroelectric memory integrated circuit
09/09/2004	US20040175848 Magnetic memory cell junction and method for forming a magnetic memory cell junction
09/09/2004	US20040175845 Method of forming a flux concentrating layer of a magnetic device
08/2004
08/31/2004	US6784510 Magnetoresistive random access memory device structures
08/26/2004	WO2004072978A2 High density and high programming efficiency mram design
08/26/2004	US20040166629 Ferroelectric memory integrated circuit with improved reliability
08/17/2004	US6778442 Method of dual cell memory device operation for improved end-of-life read margin
08/12/2004	WO2004012195A3 Efficient storage of data files received in a non-sequential manner
08/05/2004	WO2004066307A2 Stacked memory cell having diffusion barriers
08/05/2004	US20040150015 High density and high programming efficiency MRAM design
07/2004
07/22/2004	WO2004061851A2 An improved method for making high-density nonvolatile memory
07/15/2004	WO2004059651A2 Nonvolatile memory unit with specific cache
07/08/2004	US20040130929 MRAM architecture with a flux closed data storage layere
07/07/2004	EP1435099A1 Flash management system using only sequential write
07/06/2004	US6760255 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
06/2004
06/22/2004	US6754785 Switched multi-channel network interfaces and real-time streaming backup
06/16/2004	EP1428218A2 Method for identifying memory errors in electronic braking systems, computer system and the use thereof
06/01/2004	US6745310 Real time local and remote management of data files and directories and method of operating the same
06/01/2004	US6743643 Stacked memory cell having diffusion barriers
05/2004
05/20/2004	US20040095829 Ruggedised solid-state storage device
04/2004
04/29/2004	WO2004015711A3 Low leakage asymmetric sram cell devices
04/22/2004	WO2004034401A2 Dynamic memory supporting simultaneous refresh and data-access transactions
04/20/2004	CA2302015C A read-only memory and read-only memory device
04/15/2004	DE10196802T5 Rauschunterdrückung für DRAM-Architekturen mit offener Bitleitung Noise Reduction for DRAM architectures open bit line
04/13/2004	US6721222 Noise suppression for open bit line DRAM architectures
03/2004
03/30/2004	US6714446 Magnetoelectronics information device having a compound magnetic free layer
03/11/2004	WO2003025936A3 Method for identifying memory errors in electronic braking systems, computer system and the use thereof
03/11/2004	US20040046198 Stacked memory cell having diffusion barriers
02/2004
02/26/2004	US20040037127 utilize differential pFET floating gate transistors to store information
02/19/2004	WO2004015711A2 Low leakage asymmetric sram cell devices
02/19/2004	CA2495316A1 Low leakage asymmetric sram cell devices
02/11/2004	CN1474276A Data file high efficiency storage received by non-sequence mode
02/05/2004	WO2004012195A2 Efficient storage of data files received in a non-sequential manner
01/2004
01/15/2004	WO2004006262A2 Differential floating gate nonvolatile memories
01/13/2004	US6678785 Flash management system using only sequential write

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