Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2005
12/29/2005US20050289313 Synchronous flash memory with status burst output
12/29/2005US20050289294 DRAM with half and full density operation
12/29/2005US20050289292 System and method for thermal throttling of memory modules
12/29/2005US20050286667 Method and circuit for adjusting the timing of output data based on the current and future states of the output data
12/29/2005US20050286550 Method for transmitting line signals via a line device, and transmission apparatus
12/29/2005US20050286506 System and method for an asynchronous data buffer having buffer write and read pointers
12/29/2005US20050286505 Method and apparatus for generating a phase dependent control signal
12/29/2005US20050286338 Adjustable timing circuit of an integrated circuit
12/29/2005US20050286335 Memory device for reducing leakage current
12/29/2005US20050286332 Reduced area, reduced programming voltage CMOS eFUSE-based scannable non-volatile memory bitcell
12/29/2005US20050286331 Semiconductor memory device
12/29/2005US20050286330 Semiconductor memory device
12/29/2005US20050286329 Memory device
12/29/2005US20050286328 Semiconductor device and source voltage control method
12/29/2005US20050286327 Memory device with a data hold latch
12/29/2005US20050286323 Semiconductor memory device and circuit layout of dummy cell
12/29/2005US20050286322 Cascade wake-up circuit preventing power noise in memory device
12/29/2005US20050286320 Jitter and skew suppressing delay control apparatus
12/29/2005US20050286309 Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values
12/29/2005US20050286291 Dual access DRAM
12/29/2005US20050286286 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
12/29/2005US20050285862 Semiconductor device and semiconductor signal processing apparatus
12/29/2005US20050285663 Static, low-voltage fuse-based cell with high-voltage programming
12/29/2005US20050285656 Offset independent sense circuit and method
12/29/2005US20050285649 Duty cycle correction circuit for use in a semiconductor device
12/29/2005US20050285631 Data latch pre-equalization
12/29/2005US20050284929 Portable storage apparatus
12/29/2005DE102005022687A1 Semiconductor memory system has dynamic RAM (DRAM) that generates mirror mode control signal in response to chip reset signal and one of non-shared command signal received from memory controller, to operate DRAM in normal or mirror modes
12/29/2005DE102005010931A1 Mehrtordirektzugriffsspeicher Mehrtordirektzugriffsspeicher
12/29/2005DE102004027367A1 Verfahren zum Übertragen von Leitungssignalen über eine Leitungseinrichtung und Übertragungsvorrichtung A method for transmitting signals via a cable conduit means and transfer device
12/29/2005DE102004027273A1 Halbleiterbaustein mit einer ersten und mindestens einer weiteren Halbleiterschaltung und Verfahren A semiconductor device having a first and at least a further semiconductor circuit and method
12/29/2005DE102004026808A1 Abwärtskompatibler Speicherbaustein Compatible memory module downward
12/29/2005CA2570495A1 Solid-state storage device with wireless host interface
12/28/2005EP1610338A1 Steering gate and bit line segmentation in non-volatile memories
12/28/2005EP1610337A1 Non-volatile memory
12/28/2005EP1610336A1 Smart memory read out for power saving
12/28/2005EP1610335A2 Non-volatile memory and its sensing method
12/28/2005EP1609186A1 Cubic memory array
12/28/2005EP1609153A1 Simultaneous reading from and writing to different memory cells
12/28/2005CN2749024Y External digital music playing device
12/28/2005CN1714401A SDRAM address mapping optimized for two-dimensional access
12/28/2005CN1713298A Bit element switch voltage drop compensation in recording procedure of nonvolatile memory
12/28/2005CN1713128A 存储设备 Storage devices
12/27/2005US6981240 Cutting patterns for full phase shifting masks
12/27/2005US6981100 Synchronous DRAM with selectable internal prefetch size
12/27/2005US6981091 Using transfer bits during data transfer from non-volatile to volatile memories
12/27/2005US6980481 Address transition detect control circuit for self timed asynchronous memories
12/27/2005US6980480 Multi-frequency synchronizing clock signal generator
12/27/2005US6980479 Semiconductor device for domain crossing
12/27/2005US6980478 Zero-enabled fuse-set
12/27/2005US6980476 Memory device with test mode for controlling of bitline sensing margin time
12/27/2005US6980474 Semiconductor memory device
12/27/2005US6980465 Addressing circuit for a cross-point memory array including cross-point resistive elements
12/27/2005US6980461 Reference current generator, and method of programming, adjusting and/or operating same
12/27/2005US6980456 Memory with low and fixed pre-charge loading
12/27/2005US6980455 Remote sensed pre-amplifier for cross-point arrays
12/27/2005US6980454 Low-power consumption semiconductor memory device
12/27/2005US6980453 Flash memory with RDRAM interface
12/27/2005US6980040 Delay adjusting apparatus providing different delay times by producing a plurality of delay control signals
12/27/2005US6979853 DRAM memory cell and memory cell array with fast read/write access
12/27/2005CA2412169C Addressing of memory matrix
12/22/2005WO2005122177A1 Semiconductor integrated circuit
12/22/2005WO2005101977A3 Multi-factor security system with portable devices and security kernels
12/22/2005WO2005098867A3 Rewriteable electronic fuses
12/22/2005US20050283689 Error correction in ROM embedded DRAM
12/22/2005US20050283657 Semiconductor memory device
12/22/2005US20050283582 Smart memory read out for power saving
12/22/2005US20050283336 Process independent delay chain
12/22/2005US20050281175 Method of storing and reading a data bit in a phase change alloy material
12/22/2005US20050281128 Semiconductor memory apparatus and method for operating a semiconductor memory apparatus
12/22/2005US20050281124 Method for accessing a single port memory
12/22/2005US20050281122 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
12/22/2005US20050281121 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
12/22/2005US20050281120 Memory system, method and predeconding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
12/22/2005US20050281114 Shared decoupling capacitance
12/22/2005US20050281113 Data processing system and data processing method
12/22/2005US20050281112 Semiconductor memory device and refresh period controlling method
12/22/2005US20050281111 LDPC decoder
12/22/2005US20050281110 Semiconductor integrated circuit device
12/22/2005US20050281109 SRAM memory cell and method for compensating a leakage current flowing into the SRAM memory cell
12/22/2005US20050281108 Memory Module with hierarchical functionality
12/22/2005US20050281107 Semiconductor memory
12/22/2005US20050281106 Semiconductor memory device for low power consumption
12/22/2005US20050281104 Storage device
12/22/2005US20050281099 Apparatus and method for improving dynamic refresh in a memory device
12/22/2005US20050281097 System and method for equalizing high-speed data transmission
12/22/2005US20050281096 High-density memory module utilizing low-density memory components
12/22/2005US20050281090 Memory architecture with segmented writing lines
12/22/2005US20050281089 Memory card and semiconductor device
12/22/2005US20050281080 Magnetic random access memory array having bit/word lines for shared write select and read operations
12/22/2005US20050280070 Semiconductor memory device and method of manufacturing the same
12/22/2005US20050280036 Semiconductor product having a first and at least one further semiconductor circuit and method
12/22/2005DE102004025900A1 Leselatenz-Steuerschaltung Read latency control circuit
12/22/2005DE102004025893A1 Testvorrichtung mit Speicherdatenumsetzer für redundante Bit- und Wortleitungen Test device with memory data converter for redundant bit and word lines
12/22/2005DE102004025702A1 Process for the dynamic configuration of electronic circuits uses control and address inputs to a control circuit
12/21/2005EP1607979A2 Memory architecture with segmented write lines
12/21/2005EP1607978A2 Storage device
12/21/2005EP1606822A1 Universal memory device having a profile storage unit
12/21/2005EP1606821A2 An apparatus and method for a configurable mirror fast sense amplifier
12/21/2005EP1606820A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
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