Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2007
08/07/2007US7253475 Power transistor cell and power transistor component with fusible link
08/07/2007US7253457 Semiconductor device with external terminals arranged symmetrically with respect to a normal external terminal arrangement
08/02/2007WO2007086050A2 Device having an array of non-volatile memory cells and a method for altering a state of a non-volatile memory cell
08/02/2007WO2007085725A1 Prerecorded digital walkman
08/02/2007WO2007085492A1 Wire-free headset, portable media player
08/02/2007WO2006026171A3 Enhanced timing margin memory interface
08/02/2007US20070177445 Semiconductor device
08/02/2007US20070177444 Semiconductor device having super junction structure and method for manufacturing the same
08/02/2007US20070177443 Semiconductor memory device
08/02/2007US20070177442 Low voltage data path and current sense amplifier
08/02/2007US20070177439 Displaying supply information of an image forming apparatus
08/02/2007US20070177438 Method of driving transistor and shift register performing the same
08/02/2007US20070177437 Nano molecular modeling method
08/02/2007US20070177436 Memory System and Method for Two Step Memory Write Operations
08/02/2007US20070177435 System for multiple wireless local area networks
08/02/2007US20070177434 Three-level nonvolatile semiconductor memory device and associated method of operation
08/02/2007US20070177433 Method and system for data security of recording media
08/02/2007US20070177432 Phase change memory latch
08/02/2007DE102007003584A1 Phasendetektor Phase detector
08/02/2007DE102006062383A1 Halbleiterspeicherelement, System für ein Halbleiterspeicherelement und Verfahren zum Betreiben eines Halbleiterspeicherelements A semiconductor memory element system for a semiconductor memory device and method of operating a semiconductor memory device
08/02/2007DE102006050233A1 Speichermodul, Speichersteuereinheit, Speichersystem und Verfahren zum Steuern eines Speichersystems Memory module, memory controller, memory system and method for controlling a storage system
08/02/2007DE102004001577B4 Halbleiter-Speicherschaltung und Verfahren zum Betreiben derselben in einem Bereitschaftsmodus A semiconductor memory circuit and method of operating same in a standby mode
08/01/2007EP1814119A1 Semiconductor memory, memory controller and control method for semiconductor memory
08/01/2007CN2930202Y Card type electronic device
08/01/2007CN2929912Y Lound speaker with MP3 decoder and USB function
08/01/2007CN2929911Y Camera MP3 player
08/01/2007CN2929910Y Finger ring type MP3 player
08/01/2007CN2929907Y Instant listening, singing and recording kara ok device
08/01/2007CN1329923C 边界可寻址存储器 Addressable memory boundary
08/01/2007CN1329922C Semiconductor memory device
08/01/2007CN1329921C Semiconductor memory and method for entering its operation mode
08/01/2007CN1329920C A method for non-destructive readout and apparatus for use with the method
08/01/2007CN1329915C Steering gate and bit line segmentation in non-volatile memories
08/01/2007CN1329843C Information processing apparatus and method of accessing memory
08/01/2007CN101010750A MRAM sense amplifier having a precharge circuit and method for sensing
08/01/2007CN101009948A Earphone with MP3
08/01/2007CN101009577A Method and device for playing audio
08/01/2007CN101009485A Reset signal generator in semiconductor device
08/01/2007CN101009132A Memory with spatially encoded data storage
07/2007
07/31/2007US7251813 Server apparatus having function of changing over from old to new module
07/31/2007US7251757 Memory testing
07/31/2007US7251715 Double data rate scheme for data output
07/31/2007US7251714 Method and system for capturing and bypassing memory transactions in a hub-based memory system
07/31/2007US7251711 Apparatus and methods having a command sequence
07/31/2007US7251191 Method for controlling time point for data output in synchronous memory device
07/31/2007US7251190 Non-volatile semiconductor memory device
07/31/2007US7251188 Memory access interface for a micro-controller system with address/data multiplexing bus
07/31/2007US7251187 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
07/31/2007US7251186 Multi-port memory utilizing an array of single-port memory cells
07/31/2007US7251183 Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit
07/31/2007US7251182 Semiconductor memory device and semiconductor integrated circuit device
07/31/2007US7251180 Semiconductor memory device
07/31/2007US7251178 Current sense amplifier
07/31/2007US7251177 Skewed sense AMP for variable resistance memory sensing
07/31/2007US7251176 Semiconductor memory device
07/31/2007US7251175 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
07/31/2007US7251174 Semiconductor memory device for low power system
07/31/2007US7251173 Combination column redundancy system for a memory array
07/31/2007US7251172 Efficient register for additive latency in DDR2 mode of operation
07/31/2007US7251171 Semiconductor memory and system apparatus
07/31/2007US7251169 Voltage supply circuit and semiconductor memory
07/31/2007US7251168 Interface for access to non-volatile memory on an integrated circuit
07/31/2007US7251162 Nonvolatile memory with multi-frequency charge pump control
07/31/2007US7251157 Semiconductor device
07/31/2007US7251155 Device and method having a memory array storing each bit in multiple memory cells
07/31/2007US7251151 Non-volatile memory comprising means for distorting the output of memory cells
07/31/2007US7251149 Semiconductor memory device provided with a write column selection switch and a read column selection switch separately
07/31/2007US7251148 Matchline sense circuit and method
07/31/2007US7251147 Content comparator memory (CCM) device and method of operation
07/31/2007US7250809 Boosted voltage generator
07/31/2007US7250784 Integrated systems testing
07/26/2007WO2007084217A1 Random cache read using a double memory
07/26/2007WO2007059443A3 Clock signal generation techniques for memories that do not generate a strobe
07/26/2007WO2007039087A3 Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
07/26/2007US20070174909 System and method for intelligence based security
07/26/2007US20070174575 Detection circuit for mixed asynchronous and synchronous memory operation
07/26/2007US20070171760 Apparatus and method for trimming static delay of a synchronizing circuit
07/26/2007US20070171759 Semiconductor memory device, system and method of testing same
07/26/2007US20070171755 Semiconductor memory device and method therefor
07/26/2007US20070171753 Method and system for low power refresh of dynamic random access memories
07/26/2007US20070171752 Method and system for low power refresh of dynamic random access memories
07/26/2007US20070171751 Device and method for controlling refresh rate of memory
07/26/2007US20070171750 Apparatus and method for self-refreshing dynamic random access memory cells
07/26/2007US20070171749 Device having an array of non-volatile memory cells and a method for altering a state of a non-volatile memory cell
07/26/2007US20070171748 Sense amplifier circuit
07/26/2007US20070171747 Memory and method for sensing data in a memory using complementary sensing scheme
07/26/2007US20070171746 Non-volatile memory with power-saving multi-pass sensing
07/26/2007US20070171745 BLEQ driving circuit in semiconductor memory device
07/26/2007US20070171744 Memories with alternate sensing techniques
07/26/2007US20070171742 Semiconductor memory device having an open bit line structure, and method of testing the same
07/26/2007US20070171740 Semiconductor memory module and semiconductor memory device
07/26/2007US20070171738 Semiconductor memory device
07/26/2007US20070171737 Semiconductor storage device
07/26/2007US20070171735 Latency circuit for semiconductor memories
07/26/2007US20070171734 Transistor Level Shifter Circuit
07/26/2007US20070171733 Timing circuit cad
07/26/2007US20070171732 Organic memory
07/26/2007US20070171731 Leakage mitigation logic
07/26/2007US20070171691 Semiconductor device with electrically broken fuse and its manufacture method
07/26/2007DE112004001952T5 Verfahren und Schaltungskonfiguration für Mehrfachladungsrückführung während Auffrischoperationen bei einer Dram-Vorrichtung A method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device