Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2007
10/25/2007US20070247946 Bulk erase tool
10/25/2007US20070247945 Method for providing a bulk erase tool having a portion of reduced field strength
10/25/2007US20070247944 Integrated Semiconductor Memory with Refreshing of Memory Cells
10/25/2007US20070247943 Magnetic memory device and method for reading the same
10/25/2007US20070247942 Circuit and method for controlling sense amplifier of semiconductor memory apparatus
10/25/2007US20070247941 Semiconductor memory device
10/25/2007US20070247940 High speed sensing amplifier for an mram cell
10/25/2007US20070247939 Mram array with reference cell row and methof of operation
10/25/2007US20070247938 Separate sense amplifier precharge node in a semiconductor memory device
10/25/2007US20070247935 Clocked Memory System with Termination Component
10/25/2007US20070247934 High-Performance Flash Memory Data Transfer
10/25/2007US20070247933 Method of High-Performance Flash Memory Data Transfer
10/25/2007US20070247932 Shift register circuit and image display comprising the same
10/25/2007US20070247930 Dual chip package
10/25/2007US20070247929 Memory device and method of operating such
10/25/2007US20070247928 Flash memory device
10/25/2007US20070247927 Data Generator Having Stable Duration From Trigger Arrival to Data Output Start
10/25/2007US20070247926 RFID device having nonvolatile ferroelectric memory device
10/25/2007US20070247920 Data processing apparatus
10/25/2007US20070247891 Over-driven access method and device for ferroelectric memory
10/25/2007US20070247186 Semiconductor integrated circuits with power reduction mechanism
10/25/2007DE20023937U1 Universeller Abspieler für komprimierte Audioinformationen Universal compressed audio player information
10/25/2007DE19958614B4 Decodierschaltung und Decodierverfahren derselben Decoding circuit and decoding method thereof
10/25/2007DE19914986B4 Vorrichtung zum Verzögern eines Taktsignals Means for delaying a clock signal
10/25/2007DE10333280B4 Halbleiter-Speicherbauelement, Vorrichtung mit Halbleiter-Speicherbauelement und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements, wobei Speicherzellen aktiviert, und fallweise vorzeitig deaktiviert werden Be semiconductor memory device, device with semiconductor memory device and method of operating a semiconductor memory device, wherein memory cells are activated and deactivated from case to case prematurely
10/25/2007DE102007013759A1 Memory e.g. dynamic RAM, for use in electrical system, has output pointer control making output pointer to be available based on external clock signal and updating pointer based on written signals such that pointer points to valid data
10/25/2007DE102006020107B3 Data receiver for use in serial data transmission system of e.g. semiconductor memory, has sampling unit connected with data signal input for sampling data signal amplitude and amplifying sampled data signal amplitude to specific value
10/25/2007DE10051164B4 Verfahren zur Maskierung von DQ-Bits A method for masking DQ bits
10/24/2007CN200966140Y Earphone with audio source player
10/24/2007CN200966047Y A portable player with the voice communication and information transmission functions
10/24/2007CN101061550A Read method and sensing device
10/24/2007CN101061549A System and method for expanding a pulse width
10/24/2007CN101061548A Temperature based DRAM refresh
10/24/2007CN101060009A Disabling clocked standby mode based on device temperature
10/24/2007CN101060008A Multi-port memory device with serial input/output interface and control method thereof
10/24/2007CN101060007A 复合存储器芯片 Complex memory chip
10/24/2007CN101060006A Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
10/24/2007CN101060005A Multi-memory module circuit topology and method for reducing resistance incontinuity
10/24/2007CN101059782A Memory access device
10/24/2007CN101058021A Exercise assistant apparatus and method for directing exercise pace in conjunction with music
10/24/2007CN100345300C Common bit/common source line high density 1T1RR-RAM array and operation method
10/24/2007CN100345215C Sensing device for a passive matrix memory and a read method for use therewith
10/24/2007CN100345213C System and method for early write to memory by holding bitline at fixed potential
10/23/2007US7287277 Method and apparatus for controlling execution of a computer operation
10/23/2007US7287143 Synchronous memory device having advanced data align circuit
10/23/2007US7287119 Integrated circuit memory device with delayed write command processing
10/23/2007US7287115 Multi-chip package type memory system
10/23/2007US7287110 Storage device for a multibus architecture
10/23/2007US7287109 Method of controlling a memory device having a memory core
10/23/2007US7287106 Regulating real-time data capture rates to match processor-bound data consumption rates
10/23/2007US7287105 Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation
10/23/2007US7286436 High-density memory module utilizing low-density memory components
10/23/2007US7286434 Semiconductor memory device with shift register-based refresh address generation circuit
10/23/2007US7286433 Method for activating a plurality of word lines in a refresh cycle, and electronic memory device
10/23/2007US7286432 Temperature update masking to ensure correct measurement of temperature when references become unstable
10/23/2007US7286431 Memory device capable of performing high speed reading while realizing redundancy replacement
10/23/2007US7286430 Semiconductor device
10/23/2007US7286428 Offset compensated sensing for magnetic random access memory
10/23/2007US7286427 Integrated semiconductor memory device with test circuit for sense amplifier
10/23/2007US7286426 Semiconductor memory device
10/23/2007US7286425 System and method for capacitive mis-match bit-line sensing
10/23/2007US7286424 Semiconductor integrated circuit device
10/23/2007US7286423 Bit line precharge in embedded memory
10/23/2007US7286422 Memory device with built-in test function and method for controlling the same
10/23/2007US7286421 Active compensation for operating point drift in MRAM write operation
10/23/2007US7286419 Semiconductor memory device outputting identifying and roll call information
10/23/2007US7286416 Non-volatile semiconductor memory device and semiconductor memory device
10/23/2007US7286415 Semiconductor memory devices having a dual port mode and methods of operating the same
10/23/2007US7286401 Nonvolatile semiconductor memory device
10/23/2007US7286399 Dedicated redundancy circuits for different operations in a flash memory device
10/23/2007US7286383 Bit line sharing and word line load reduction for low AC power SRAM architecture
10/23/2007US7286377 Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
10/23/2007US7285983 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
10/23/2007US7285811 MRAM device for preventing electrical shorts during fabrication
10/23/2007US7285464 Nonvolatile memory cell comprising a reduced height vertical diode
10/18/2007US20070245071 Random access interface in a serial memory device
10/18/2007US20070242553 Multi-port memory device with serial input/output interface and control method thereof
10/18/2007US20070242547 Self refresh operation of semiconductor memory device
10/18/2007US20070242546 Semiconductor memory device
10/18/2007US20070242545 Semiconductor memory device
10/18/2007US20070242544 Method and system for providing directed bank refresh for volatile memories
10/18/2007US20070242543 Dram bitline precharge scheme
10/18/2007US20070242542 Memory
10/18/2007US20070242541 Sense amplifier with reduced current consumption for semiconductors memories
10/18/2007US20070242540 Semiconductor memory device with temperature sensing device and operation thereof
10/18/2007US20070242539 Semiconductor memory device
10/18/2007US20070242538 Apparatus and methods for determining memory device faults
10/18/2007US20070242537 Radiation-hardened memory element with multiple delay elements
10/18/2007US20070242535 Semiconductor memory device and defect remedying method thereof
10/18/2007US20070242533 Memory Access Apparatus
10/18/2007US20070242532 Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time
10/18/2007US20070242531 Write apparatus for ddr sdram semiconductor memory device
10/18/2007US20070242530 Memory controller for supporting double data rate memory and related method
10/18/2007US20070242529 Method and Apparatus for Accessing Contents of Memory Cells
10/18/2007US20070242528 Nonvolatile semiconductor memory device
10/18/2007US20070242527 Semiconductor memory device for storing multilevel data
10/18/2007US20070242526 Semiconductor memory and read method of the same
10/18/2007US20070242520 Voltage regulator having a low noise discharge switch for non-volatile memories, in particular for discharging word lines from negative voltages
10/18/2007DE19962509B4 Bitleitungsleseverstärker für eine Halbleiterspeicher-Vorrichtung Bit line sense amplifier for a semiconductor memory device
10/18/2007DE19750927B4 Verfahren zum kontinuierlichen Auslesen einer Datenfolge aus einem Speicher A method for continuously reading out a data string from a storage
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