Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
09/2007
09/18/2007US7271620 Variable impedance output buffer
09/18/2007US7271016 Methods and apparatus for a flexible circuit interposer
09/13/2007WO2007103045A2 Nand memory device column charging
09/13/2007US20070214492 Personal lifestyle device
09/13/2007US20070214337 Data transfer control method, and peripheral circuit, data processor and data processing system for the method
09/13/2007US20070211556 Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof
09/13/2007US20070211554 Memory with serial input-output terminals for address and data and method therefor
09/13/2007US20070211550 Non-skipping auto-refresh in a DRAM
09/13/2007US20070211549 Semiconductor memory, memory system, and operation method of semiconductor memory
09/13/2007US20070211548 Temperature determination and communication for multiple devices of a memory module
09/13/2007US20070211547 Semiconductor device
09/13/2007US20070211544 Semiconductor device
09/13/2007US20070211543 Semiconductor device with non-volatile memory and random access memory
09/13/2007US20070211542 Multi-probe for writing and reading data and method of operating the same
09/13/2007US20070211512 Ferroelectric memory device
09/13/2007DE10302224B4 Integrierter Speicher Built-in Memory
09/13/2007DE102006048846A1 Eichschaltung und dieselbe enthaltende Halbleitervorrichtung Calibration circuit and containing the same semiconductor device
09/12/2007EP1831892A1 System for performing fast testing during flash reference cell setting
09/12/2007EP1741107A4 Refreshing data stored in a flash memory
09/12/2007EP1709541A4 Apparatus and method for use of memory devices for audio
09/12/2007EP1614044A4 Sampling tuning system
09/12/2007CN200947354Y MP3 player
09/12/2007CN200946839Y Microwave oven with MP3 playing function
09/12/2007CN101036174A Enhanced techniques for using core based nodes for state transfer
09/12/2007CN101034586A Circuit and method for detecting synchronous mode in a semiconductor memory apparatus
09/12/2007CN101034585A SRAM system circuit without sensitive amplifier
09/12/2007CN101034425A Portable date storing device
09/12/2007CN101034356A Memory device
09/12/2007CN100337449C Clock resynchronizer
09/12/2007CN100337223C Structure capable of making burning program directly on the mainboard
09/12/2007CN100337197C Guide program recorder and method for guarantee of online upgrading thereof
09/11/2007US7269765 Method and apparatus for storing failing part locations in a module
09/11/2007US7269754 Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
09/11/2007US7269742 Microprocessor configuration with encryption
09/11/2007US7269700 Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
09/11/2007US7269699 Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
09/11/2007US7269686 Synchronous memory open page register
09/11/2007US7269481 Method and apparatus for memory bandwidth thermal budgetting
09/11/2007US7269091 Word line driver circuitry and methods for using the same
09/11/2007US7269087 Semiconductor memory device
09/11/2007US7269085 Non volatile semiconductor memory device having a multi-bit cell array
09/11/2007US7269084 Semiconductor memory device
09/11/2007US7269082 Chip enable control circuit, memory control circuit, and data processing system
09/11/2007US7269078 Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits
09/11/2007US7269077 Memory architecture of display device and memory writing method for the same
09/11/2007US7269076 Low power consumption data input/output circuit of embedded memory device and data input/output method of the circuit
09/11/2007US7269075 Method and apparatus for simultaneous differential data sensing and capture in a high speed memory
09/11/2007US7269064 Method of controlling page buffer having dual register and circuit thereof
09/11/2007US7269059 Magnetic recording element and device
09/11/2007US7269052 Device selection circuitry constructed with nanotube technology
09/11/2007US7269043 Memory module and impedance calibration method of semiconductor memory device
09/11/2007US7269042 Memory stacking system and method
09/11/2007US7268602 Method and apparatus for accommodating delay variations among multiple signals
09/11/2007US7268531 Apparatus for improving stability and lock time for synchronous circuits
09/11/2007US7268044 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
09/07/2007WO2007100694A2 Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
09/06/2007US20070206434 Memory with multi-page read
09/06/2007US20070206429 Memory component with multiple delayed timing signals
09/06/2007US20070206428 High-speed phase-adjusted quadrature data rate (qdr) transceiver and method thereof
09/06/2007US20070206426 System for performing read operation on non-volatile storage with compensation for coupling
09/06/2007US20070206425 Semiconductor memory device
09/06/2007US20070206420 Mode selection in a flash memory device
09/06/2007US20070206407 Spin Based Memory Coupled to CMOS Amplifier
09/06/2007US20070206403 Semiconductor memory device and semiconductor integrated circuit system
09/06/2007DE102004059124B4 Prozessorbasierende Struktur und Verfahren zum Laden unausgerichteter Daten Processor-based structure and method for loading unaligned data
09/05/2007EP1830365A1 Nonvolatile semiconductor memory devices
09/05/2007EP1830364A1 Nonvolatile semiconductor memory devices
09/05/2007EP1830363A1 Synchronization type storage device and control method thereof
09/05/2007EP1830241A1 Integrated circuit I/O using a high performance bus interface
09/05/2007EP1829045A1 Pipelined programming of non-volatile memories using early data
09/05/2007EP1829042A1 Data relocation in a memory system
09/05/2007EP1829041A1 Memory access using multiple activated memory cell rows
09/05/2007EP1828896A2 High speed and low power sram macro architecture and method
09/05/2007EP1828716A1 System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices
09/05/2007EP1552314A4 Sense amplifier with configurable voltage swing control
09/05/2007CN200944318Y Flash disk
09/05/2007CN200944317Y USB audio system
09/05/2007CN200944316Y Card reader for audio equipment
09/05/2007CN200944234Y Novel electronic media literature reading device
09/05/2007CN200944065Y Mobile storage device capable of measuring temperature
09/05/2007CN101031895A Simultaneous external read operation during internal programming in a flash memory device
09/05/2007CN101030765A 信号放大器 Signal amplifier
09/05/2007CN101030445A Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods
09/05/2007CN101030442A Memory module
09/05/2007CN101030441A Method and apparatus for reading and sampling data of DDR and DDR2 memory controller
09/05/2007CN101030440A Micro-flash disk for determining data safety
09/05/2007CN101030439A Multi-port memory device and method of controlling the same
09/05/2007CN101030438A Multiple matching detection circuit and method for content addressable memory
09/05/2007CN101030424A Song playing method
09/05/2007CN101030381A Method and apparatus for extracting MP3 file sampling rate
09/05/2007CN100336134C Semiconductor circuit and method of controlling same
09/05/2007CN100336132C Read-out amplifier for memory equipment
09/04/2007US7266842 Control function implementing selective transparent data authentication within an integrated system
09/04/2007US7266759 Semiconductor integrated circuit device and error checking and correcting method thereof
09/04/2007US7266747 Error correction scheme for memory
09/04/2007US7266732 MRAM with controller
09/04/2007US7266714 Method an apparatus for adjusting the time of a clock if it is determined that the degree of adjustment is within a limit based on the clocks initial time
09/04/2007US7266662 Input/output data pipeline circuit of semiconductor memory device and the semiconductor memory device
09/04/2007US7266037 Semiconductor memory device with hierarchical I/O line architecture
09/04/2007US7266035 Self-aligned row-by-row dynamic VDD SRAM