Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2007
11/29/2007US20070273409 Offset independent sense circuit and method
11/29/2007DE102006062725A1 Memory chip e.g. Dynamic RAM-chip, for use in e.g. computer system, has timer controlling output buffer such that buffer releases buffer data, where chip determines latency period from provision of signals upto availability of read data
11/29/2007DE102006022867A1 Read-out circuit for ROM, has input, in which read signal is coupled and high signal level and another low signal level related to reference potential depending on information contained
11/28/2007EP1614118A4 Low-voltage sense amplifier and method
11/28/2007EP1532737B1 Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line
11/28/2007CN200983668Y Ear cover earphone with MP3 player
11/28/2007CN200983266Y Music generation U disk
11/28/2007CN200983265Y Access device of improved IC burning device
11/28/2007CN200983252Y Aviation carried digital recordable video player
11/28/2007CN200983177Y Banknote checker
11/28/2007CN200981248Y Dish frying technique prompting knife
11/28/2007CN200980538Y Drinking cup with music indicating function
11/28/2007CN200980385Y Bracelets with recording and playing function
11/28/2007CN101079326A Semiconductor memory device testing on/off state of on-die-termination circuit during data read mode, and test method of the state of on-die-termination circuit
11/28/2007CN101079313A First in first out memory without read delay
11/28/2007CN101079312A Multimedia broadcasting device with voice prompt operation and its method
11/28/2007CN101079311A Audio control operated multimedia broadcasting device and its audio control operation method
11/28/2007CN101079310A Memory device with shared reference and method
11/28/2007CN101079307A Portable multimedia apparatus audio frequency music searching method
11/28/2007CN101078870A Self-imaging and voice system for relief
11/28/2007CN100352163C Static selection circuit with high reliability and cow-power consumption
11/28/2007CN100351950C Nonvolatile semiconductor storage apparatus
11/28/2007CN100351948C Semiconductor memory
11/28/2007CN100351944C Dynamic memory cell refreshing method for memory circuit, and memory circuit
11/28/2007CN100351943C Mixed resistive cross point memory unit array and its making process
11/28/2007CN100351733C Clock control in sequential circuit for low-power operation and circuit conversion to low-power seqential circuit
11/27/2007US7302545 Method and system for fast data access using a memory array
11/27/2007US7302505 Receiver multi-protocol interface and applications thereof
11/27/2007US7302163 Information processing apparatus and recording control method including erroneous-erasure prevention feature
11/27/2007US7301848 Apparatus and method for supplying power in semiconductor device
11/27/2007US7301844 Semiconductor device
11/27/2007US7301843 Semiconductor memory device having complete hidden refresh function
11/27/2007US7301842 Synchronous pseudo static random access memory
11/27/2007US7301841 Circuit and method for selecting test self-refresh period of semiconductor memory device
11/27/2007US7301840 Semiconductor memory device
11/27/2007US7301839 Read operation for non-volatile storage that includes compensation for coupling
11/27/2007US7301838 Sense amplifier circuitry and architecture to write data into and/or read from memory cells
11/27/2007US7301837 Error test for an address decoder of a non-volatile memory
11/27/2007US7301836 Feature control circuitry for testing integrated circuits
11/27/2007US7301835 Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
11/27/2007US7301834 Semiconductor memory
11/27/2007US7301833 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device
11/27/2007US7301831 Memory systems with variable delays for write data signals
11/27/2007US7301830 Semiconductor memory device and semiconductor device and semiconductor memory device control method
11/27/2007US7301828 Decoding techniques for read-only memory
11/27/2007US7301827 Semiconductor memory device
11/27/2007US7301826 Memory, processing system and methods for use therewith
11/27/2007US7301825 Method of controlling copy-back operation of flash memory device including multi-level cells
11/27/2007US7301822 Multi-boot configuration of programmable devices
11/27/2007US7301819 ROM with a partitioned source line architecture
11/27/2007US7301807 Writable tracking cells
11/27/2007US7301802 Circuit arrays having cells with combinations of transistors and nanotube switching elements
11/27/2007US7301793 Semiconductor memory device
11/22/2007WO2007133963A2 Nonvolatile memory with convolutional coding for error correction
11/22/2007US20070271598 Systems and methods for user access authentication based on network access point
11/22/2007US20070268776 Semiconductor memory device and test method thereof
11/22/2007US20070268772 Semiconductor memory and operating method of same
11/22/2007US20070268768 Semiconductor memory
11/22/2007US20070268766 Semiconductor memory and refresh cycle control method
11/22/2007US20070268765 Integrated Circuit Memory Device Having Dynamic Memory Bank Count and Page Size
11/22/2007US20070268764 Low voltage sense amplifier and sensing method
11/22/2007US20070268763 Method for controlling precharge timing of memory device and apparatus thereof
11/22/2007US20070268762 Semiconductor memory and method for testing the same
11/22/2007US20070268761 Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same
11/22/2007US20070268760 Semiconductor memory in which fuse data transfer path in memory macro is branched
11/22/2007US20070268759 Systems for and methods of asset management in a waste management service environment
11/22/2007US20070268758 Memory Array with Psedudo Single Bit Memory Cell and Method
11/22/2007US20070268757 High voltage detecting circuit for semiconductor memory device and method of controlling the same
11/22/2007US20070268756 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
11/22/2007US20070268755 Memory circuit
11/22/2007US20070268752 Nonvolatile semiconductor memory device
11/22/2007US20070268751 Flash memory device and related high voltage generating circuit
11/22/2007US20070268745 Method of storing data in a multi-bit-cell flash memory
11/22/2007DE19581689B4 Einrichtung und Verfahren zum Erhöhen der Burst-Rate von EDO-DRAMs in einem Computersystem Means and method for increasing the rate of burst EDO DRAMs in a computer system
11/22/2007DE112005003277T5 Fühlerverstärker mit großem Spannungshub Sense amplifier with a large voltage swing
11/22/2007DE102007013760A1 Filterung der Bitposition in einem Speicher Filtering the bit position in a memory
11/22/2007DE10156358B4 Vorrichtung und Verfahren zum Übertragen von Fehlerinformationen, die beim Testen eines Speicherbausteins für eine nachfolgende Redundanzanalyse erhalten werden, in einen Fehlerspeicher Apparatus and method for transmitting error information obtained during testing of a memory device for subsequent redundancy analysis, in a fault memory
11/22/2007DE10149584B4 Verzögerungsregelkreis Delay locked loop
11/22/2007DE10046578B4 Integrierter Speicherbaustein und Speicheranordnung mit mehreren Speicherbausteinen sowie Verfahren zum Betrieb einer solchen Speicheranordnung Built-in memory chip and memory array having a plurality of memory devices and methods for operating such a memory array
11/22/2007DE10042388B4 Nichtflüchtiger ferroelektrischer Speicher Non-volatile ferroelectric memory
11/21/2007EP1858027A1 A sensing circuit for semiconductor memories
11/21/2007EP1858026A1 Semiconductor memory device with reduced current consumption
11/21/2007EP1858022A2 Semiconductor memory and operating method of same
11/21/2007EP1858021A2 Phase change memory having temperature budget sensor
11/21/2007EP1858009A1 Method of recording control information on multi layer recording medium, multi layer recording medium and apparatus thereof
11/21/2007EP1477901B1 External connection device, host device, and data communication system
11/21/2007CN200980156Y An earphone with MP3 player
11/21/2007CN200979804Y A multifunctional three-in-one electronic product
11/21/2007CN200979623Y Glasses with bluetooth device
11/21/2007CN101075477A Semiconductor memory operated by internal and external refresh
11/21/2007CN101075475A 多端口半导体器件及其方法 Semiconductor device and method of the multi-port
11/21/2007CN101075474A Semiconductor memory and operating method of same
11/21/2007CN101075458A Method and device for controlling MP3 decode and inputting data to buffer
11/21/2007CN100350613C Programmable memory address and decode circuits with ultra thin vertical body transistors
11/21/2007CN100350507C Semiconductor stroage device
11/21/2007CN100350501C Low-voltage conrol method and device
11/21/2007CN100350494C External storage device and its control device and data transmitting and receiving device
11/21/2007CN100350402C A memory and an adaptive timing system for controlling access to the memory
11/21/2007CN100350400C Adaptive throttling memory accesses, such as throttling RDRAm accesses in real-time system
11/20/2007US7299329 Dual edge command in DRAM
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