Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2007
12/27/2007US20070297258 Semiconductor memory device and self-refresh method therefor
12/27/2007US20070297257 Semiconductor memory device capable of canceling out noise development
12/27/2007US20070297256 Systems and Methods for Data Transfers Between Memory Cells
12/27/2007US20070297255 Semiconductor memory tester
12/27/2007US20070297254 Method to Identify or Screen VMIN Drift on Memory Cells During Burn-In or Operation
12/27/2007US20070297252 Integrated circuit having memory array including ECC and/or column redundancy, and method of programming, controlling and/or operating same
12/27/2007US20070297251 Semiconductor memory device having memory block configuration
12/27/2007US20070297250 Data processing apparatus and method using FIFO device
12/27/2007US20070297249 Low-power SRAM memory cell
12/27/2007US20070297248 System and Method for Adjusting Compensation Applied to a Signal Using Filter Patterns
12/27/2007US20070297247 Method for programming non-volatile memory using variable amplitude programming pulses
12/27/2007US20070297238 Voltage regulator for flash memory device
12/27/2007US20070297230 Non-volatile memory structure
12/27/2007US20070297229 Flash memory device including multi-buffer block
12/27/2007US20070297221 Memory cell programmed using a temperature controlled set pulse
12/27/2007US20070297217 Method and circuit arrangement for operating a volatile random access memory as a detector
12/27/2007US20070297208 Semiconductor memory device
12/27/2007US20070296470 Semiconductor integrated circuit controlling output impedance and slew rate
12/27/2007US20070296019 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
12/27/2007DE112006000217T5 Anschlussflächennahe Ordnungslogik Pad close-order logic
12/27/2007DE10345520B4 Verfahren zum Betrieb einer Charge-Trapping-Speicherzelle Method of operating a charge-trapping memory cell
12/27/2007DE10318771B4 Integrierte Speicherschaltung mit einer Redundanzschaltung sowie ein Verfahren zum Ersetzen eines Speicherbereichs An integrated circuit memory having a redundancy circuit and a method for replacing a memory area
12/27/2007DE102006041018B3 Storage circuit has multiple parallel bit lines, which are connected to storage cells, and multiple switches which are connected with corresponding pair of bit lines of multiple bit lines
12/27/2007DE102005040109B4 Halbleiterspeicherchip The semiconductor memory chip
12/27/2007DE102004032402B4 Speichercontroller mit mehreren parallelen Transferblöcken Memory controller with multiple parallel transfer blocks
12/26/2007EP1870902A2 Semiconductor memory device and storage method thereof
12/26/2007EP1870901A1 Page buffer for multi-level nand flash memories
12/26/2007EP1297535B1 Reference cell for high speed sensing in non-volatile memories
12/26/2007CN200997672Y Intelligent microphne with memory rebroadcasting function
12/26/2007CN200997310Y Memory with 1394 interface
12/26/2007CN200997288Y Phonetic reporting musical playing system
12/26/2007CN101095196A Multi-mode memory
12/26/2007CN101095195A Complimentary lateral nitride transistors
12/26/2007CN101094360A Storage device and method of controlling access
12/26/2007CN101093720A Memory device with multiple partitions
12/26/2007CN101093719A Method for protecting hearing ability, and audio playing system with function of protecting hearing ability
12/26/2007CN101093718A Memory interface arrangement and memory data access method applied on same
12/26/2007CN101093717A Input/output agent having multiple secondary ports
12/26/2007CN101093716A Memory cell access circuit
12/26/2007CN101093715A Power saving in a thermal sensor
12/26/2007CN101093712A Device of combining MP3 with negative ion generator
12/26/2007CN101093711A A player
12/26/2007CN101093700A Method for backup data
12/26/2007CN101093677A Method of recording/reproducing data on/from a multi layer recording medium, and apparatus thereof
12/26/2007CN101093674A Method of recording/reproducing data on/from a multi layer recording medium, and apparatus thereof
12/25/2007US7313715 Memory system having stub bus configuration
12/25/2007US7313647 Storage and reproduction apparatus
12/25/2007US7313644 Memory device interface
12/25/2007US7313049 Output circuit of a memory and method thereof
12/25/2007US7313047 Dynamic semiconductor memory with improved refresh mechanism
12/25/2007US7313046 Semiconductor memory devices in which the number of memory banks to be refreshed may be changed and methods of operating the same
12/25/2007US7313045 Dynamic semiconductor storage device
12/25/2007US7313044 Integrated semiconductor memory with temperature-dependent voltage generation
12/25/2007US7313043 Magnetic Memory Array
12/25/2007US7313042 Thin film magnetic memory device having an improved read operation margin
12/25/2007US7313041 Sense amplifier circuit and method
12/25/2007US7313040 Dynamic sense amplifier for SRAM
12/25/2007US7313039 Method for analyzing defect of SRAM cell
12/25/2007US7313038 Nonvolatile memory including a verify circuit
12/25/2007US7313036 Memory device having open bit line architecture for improving repairability and method of repairing the same
12/25/2007US7313035 Methods and apparatus for improved memory access
12/25/2007US7313034 Low supply voltage temperature compensated reference voltage generator and method
12/25/2007US7313033 Random access memory including first and second voltage sources
12/25/2007US7313031 Information processing apparatus and method, memory control device and method, recording medium, and program
12/25/2007US7313028 Method for operating page buffer of nonvolatile memory device
12/25/2007US7313023 Partition of non-volatile memory array to reduce bit line capacitance
12/25/2007US7312641 Sense amplifiers with high voltage swing
12/25/2007US7312627 Decoding circuit for on die termination in semiconductor memory device and its method
12/25/2007US7312499 Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card
12/25/2007US7312109 Methods for fabricating fuse programmable three dimensional integrated circuits
12/21/2007WO2007033357A3 Semiconductor memory with reset function
12/20/2007US20070294746 Wireless authentication method and wireless authentication system
12/20/2007US20070294462 Memory device including self-id information
12/20/2007US20070291577 System with controller and memory
12/20/2007US20070291575 Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands and Related Methods
12/20/2007US20070291573 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same
12/20/2007US20070291568 Apparatus and method for controlling refresh operation of semiconductor integrated circuit
12/20/2007US20070291567 System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates
12/20/2007US20070291566 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates
12/20/2007US20070291565 Architecture and method for NAND flash memory
12/20/2007US20070291564 Semiconductor device
12/20/2007US20070291561 Sense-amplifier assist (saa) with power-reduction technique
12/20/2007US20070291560 Method and system for improving reliability of memory device
12/20/2007US20070291559 Semiconductor device with delay section
12/20/2007US20070291558 Data strobe signal generator for generating data strobe signal based on adjustable preamble value and semiconductor memory device with the same
12/20/2007US20070291557 Stacked semiconductor device
12/20/2007US20070291555 Method and apparatus for timing adjustment
12/20/2007US20070291554 Memory with Clock-Controlled Memory Access and Method of Operating the Same
12/20/2007US20070291553 Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same
12/20/2007US20070291550 Method and apparatus for high voltage operation for a high performance semiconductor memory device
12/20/2007US20070291542 Programming method for NAND flash
12/20/2007US20070291529 Semiconductor memory device
12/20/2007US20070291528 Method and apparatus for improving SRAM cell stability by using boosted word lines
12/20/2007US20070290721 Method and apparatus for amplifying a regulated differential signal to a higher voltage
12/20/2007DE102005053486B4 Schaltungsanordnung zur Erzeugung eines n-Bit Ausgangszeigers, Halbleiterspeicher und Verfahren Circuit arrangement for generating an n-bit output pointer, the semiconductor memory and method
12/20/2007DE102004051152B4 NOR-Speicheranordnung von resistiven Speicherelementen NOR memory array of resistive memory elements
12/19/2007EP1868187A1 Method of recording/reproducing data on/from a multi layer recording medium, and apparatus thereof
12/19/2007EP1868186A1 Method for recording control information on a recording medium, recording medium and apparatus thereof
12/19/2007EP1866927A1 Y-mux splitting scheme
12/19/2007EP1496518B1 Storage device using resistance varying storage element and reference resistance value decision method for the device
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