| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 10/27/2004 | CN1173409C Multi-stage quick EEPROM unit and manufacture thereof |
| 10/27/2004 | CN1173402C Semiconductor integrated circuit |
| 10/27/2004 | CN1173392C Equipment and method for screening test of fault leakage of storage device |
| 10/27/2004 | CN1173367C Semiconductor memory device |
| 10/26/2004 | US6810497 Semiconductor integrated circuit compensating variations of delay time |
| 10/26/2004 | US6810444 Memory system allowing fast operation of processor while using flash memory incapable of random access |
| 10/26/2004 | US6809990 Delay locked loop control circuit |
| 10/26/2004 | US6809989 Semiconductor storage device |
| 10/26/2004 | US6809984 Multiport memory circuit composed of 1Tr-1C memory cells |
| 10/26/2004 | US6809982 Defective cell remedy method capable of automatically cutting capacitor fuses within the fabrication process |
| 10/26/2004 | US6809981 Wordline driven method for sensing data in a resistive memory array |
| 10/26/2004 | US6809980 Limiter for refresh signal period in DRAM |
| 10/26/2004 | US6809979 Complete refresh scheme for 3T dynamic random access memory cells |
| 10/26/2004 | US6809978 Implementation of a temperature sensor to control internal chip voltages |
| 10/26/2004 | US6809977 Method for reading and writing memory cells of spatial light modulators used in display systems |
| 10/26/2004 | US6809976 Non-volatile semiconductor memory device conducting read operation using a reference cell |
| 10/26/2004 | US6809975 Semiconductor memory device having test mode and memory system using the same |
| 10/26/2004 | US6809972 Circuit technique for column redundancy fuse latches |
| 10/26/2004 | US6809968 SRAM array with temperature-compensated threshold voltage |
| 10/26/2004 | US6809962 Storing data in-non-volatile memory devices |
| 10/26/2004 | US6809959 Hybrid semiconductor—magnetic spin based memory with low transmission barrier |
| 10/26/2004 | US6809958 MRAM parallel conductor orientation for improved write performance |
| 10/26/2004 | US6809957 Memory cells enhanced for resistance to single event upset |
| 10/26/2004 | US6809954 Circuit and method for reducing access transistor gate oxide stress |
| 10/26/2004 | US6809951 Ferroelectric semiconductor memory |
| 10/26/2004 | US6809949 Ferroelectric memory |
| 10/26/2004 | US6809948 Mask programmable read-only memory (ROM) cell |
| 10/26/2004 | US6809947 Multi-level semiconductor memory architecture and method of forming the same |
| 10/26/2004 | US6809946 Semiconductor memory device and method of controlling the same |
| 10/26/2004 | US6809914 Use of DQ pins on a ram memory chip for a temperature sensing protocol |
| 10/26/2004 | US6809578 Stable voltage generating circuit |
| 10/26/2004 | US6809576 Semiconductor integrated circuit device having two types of internal power supply circuits |
| 10/26/2004 | US6809554 Semiconductor integrated circuit having a voltage conversion circuit |
| 10/26/2004 | US6809546 On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same |
| 10/26/2004 | US6809401 Memory, writing apparatus, reading apparatus, writing method, and reading method |
| 10/26/2004 | US6809399 Semiconductor integrated circuit device and process for manufacturing the same |
| 10/26/2004 | US6809362 Multiple data state memory cell |
| 10/26/2004 | US6809361 Magnetic memory unit and magnetic memory array |
| 10/26/2004 | US6809336 Semiconductor device comprising sense amplifier and manufacturing method thereof |
| 10/26/2004 | US6808990 Random access memory cell and method for fabricating same |
| 10/26/2004 | US6808940 Magnetic shielding for reducing magnetic interference |
| 10/26/2004 | US6808325 Keyboard with an internal printer |
| 10/21/2004 | WO2004090909A1 Information memory device and its operation method |
| 10/21/2004 | WO2004090907A1 Leakage current reduction for cmos memory circuits |
| 10/21/2004 | WO2004090905A2 Three-dimensional memory device incorporating segmented bit line memory array |
| 10/21/2004 | WO2004040647A9 Ferroelectric memory cell |
| 10/21/2004 | US20040210802 Redundancy register architecture for soft-error tolerance and methods of making the same |
| 10/21/2004 | US20040210733 Integrated circuit having a memory cell array capable of simultaneously performing a data read operation and a data write operation |
| 10/21/2004 | US20040210728 Data processor memory circuit |
| 10/21/2004 | US20040210710 Method for adaptive control of DRAM refresh interval |
| 10/21/2004 | US20040210709 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
| 10/21/2004 | US20040209490 Modules having a plurality of contacts along edges thereof configured to conduct signals to the modules and further having a plurality of contacts along edges thereof configured to conduct signals from the modules |
| 10/21/2004 | US20040208076 Semiconductor memory device with simple refresh control |
| 10/21/2004 | US20040208075 Refresh clock generator |
| 10/21/2004 | US20040208074 Method and regulating circuit for refreshing dynamic memory cells |
| 10/21/2004 | US20040208073 DRAM memory with a shared sense amplifier structure |
| 10/21/2004 | US20040208071 Semiconductor memory device |
| 10/21/2004 | US20040208064 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation |
| 10/21/2004 | US20040208061 Non-volatile semiconductor memory device and electric device with the same |
| 10/21/2004 | US20040208057 Method of programming dual cell memory device to store multiple data states per cell |
| 10/21/2004 | US20040208056 Integrated circuit memory devices and methods of programming the same in which the current drawn during a programming operation is independent of the data to be programmed |
| 10/21/2004 | US20040208055 Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric |
| 10/21/2004 | US20040208054 Magnetic random access memory |
| 10/21/2004 | US20040208053 High output nonvolatile magnetic memory |
| 10/21/2004 | US20040208052 Thin film magnetic memory device capable of conducting stable data read and write operations |
| 10/21/2004 | US20040208049 Semiconductor memory device including a double-gate dynamic random access memory cell having reduced current leakage |
| 10/21/2004 | US20040208046 Semiconductor integrated circuit |
| 10/21/2004 | US20040208045 Column select circuit of ferroelectric memory |
| 10/21/2004 | US20040208044 Over-driven access method and device for ferroelectric memory |
| 10/21/2004 | US20040208043 Feram memory device |
| 10/21/2004 | US20040208041 Ferroelectric memory device and display driver IC |
| 10/21/2004 | US20040208038 Phase change-type memory element and process for producing the same |
| 10/21/2004 | US20040208037 Distributed, highly configurable modular predecoding |
| 10/21/2004 | US20040208036 Static random access memory system with compensating-circuit for bitline leakage |
| 10/21/2004 | US20040207688 Printhead assembly for a wallpaper printer |
| 10/21/2004 | US20040207461 Internal step-down power supply circuit |
| 10/21/2004 | US20040207458 Voltage booster power supply circuit |
| 10/21/2004 | US20040207380 Reference voltage generating circuit capable of controlling temperature dependency of reference voltage |
| 10/21/2004 | US20040207100 Semiconductor latches and sram devices |
| 10/21/2004 | US20040207086 Magnetically lined conductors |
| 10/21/2004 | US20040207038 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement |
| 10/21/2004 | US20040207025 Data processor |
| 10/21/2004 | US20040207011 Semiconductor device, semiconductor storage device and production methods therefor |
| 10/21/2004 | US20040207003 Byte-operational nonvolatile semiconductor memory device |
| 10/21/2004 | US20040206994 MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJS) and method for fabricating the same |
| 10/21/2004 | US20040206992 Low switching field magnetic element |
| 10/21/2004 | US20040205958 Methods for fabricating MRAM device structures |
| 10/21/2004 | DE19727262B4 Halbleiterspeichervorrichtung mit über Leckdetektionsmittel gesteuerter Substratspannungserzeugungsschaltung A semiconductor memory device with more than leak detection means controlled substrate voltage generating circuit |
| 10/21/2004 | DE10358963A1 Verfahren zum Herstellen einer MTJ-Zelle eines magnetischen Direktzugriffsspeichers A method for producing an MTJ cell of a magnetic random access memory |
| 10/21/2004 | DE10346559A1 Dateninvertierungsschaltung und Halbleitervorrichtung Data inverting circuit and semiconductor device |
| 10/21/2004 | DE102004016403A1 Halbleiterspeicherbaustein sowie zugehörige Betriebs- und Leseverfahren Semiconductor memory device and associated operating and reading method |
| 10/21/2004 | DE102004010706A1 Selbsttrimmender Spannungsgenerator Self-trimming final voltage generator |
| 10/20/2004 | EP1469481A2 Apparatus and method for managing bad blocks in a flash memory |
| 10/20/2004 | EP1468423A2 Array-based architecture for molecular electronics |
| 10/20/2004 | EP1468422A1 Pcram rewrite prevention |
| 10/20/2004 | EP1468421A1 Method and apparatus to program a phase change memory |
| 10/20/2004 | EP1344222B1 Method for reading out or in a status from or to a ferroelectrical transistor of a memory cell and memory matrix |
| 10/20/2004 | EP0948792B1 Method and apparatus for sharing sense amplifiers between memory banks |
| 10/20/2004 | CN1539147A Random-access memory devices comprising deoded buffer |
| 10/20/2004 | CN1538539A Method for forming MTJ of magnetic RAM |