Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2004
11/02/2004US6813189 System for using a dynamic reference in a double-bit cell memory
11/02/2004US6813181 Circuit configuration for a current switch of a bit/word line of a MRAM device
11/02/2004US6813180 Four terminal memory cell, a two-transistor sram cell, a sram array, a computer system, a process for forming a sram cell, a process for turning a sram cell off, a process for writing a sram cell and a process for reading data from a sram cell
11/02/2004US6813177 Method and system to store information
11/02/2004US6813176 Method of retaining memory state in a programmable conductor RAM
11/02/2004US6812799 Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
11/02/2004US6812759 DLL circuit capable of preventing locking in an antiphase state
11/02/2004US6812748 Semiconductor device having substrate potential detection circuit less influenced by change in manufacturing conditions
11/02/2004US6812743 Input buffer of differential amplification type in semiconductor device
11/02/2004US6812565 Semiconductor device and a method of manufacturing the same
11/02/2004US6812538 MRAM cells having magnetic write lines with a stable magnetic state at the end regions
11/02/2004US6812537 Magnetic memory and method of operation thereof
11/02/2004US6812529 Suppression of cross diffusion and gate depletion
11/02/2004US6812511 Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
11/02/2004US6812509 Organic ferroelectric memory cells
11/02/2004US6812084 Adaptive negative differential resistance device
11/02/2004US6812040 Method of fabricating a self-aligned via contact for a magnetic memory element
11/02/2004CA2198839C Enhanced asic process cell
10/2004
10/28/2004WO2004093139A2 Memory device with sense amplifier and self-timed latch
10/28/2004WO2004093103A1 Low switching field magnetic element
10/28/2004WO2004093092A1 Magnetic memory cell including a fuse element for disconnecting the defective magnetic element
10/28/2004WO2004093091A1 Nonvolatile semiconductor storage device
10/28/2004WO2004093090A1 Read and erase verify methods and circuits suitable for low voltage non-volatile memories
10/28/2004WO2004093089A1 Dynamic semiconductor storage device
10/28/2004WO2004093088A1 Ferroelectric memory and method for reading its data
10/28/2004WO2004093087A1 Magnetic memory device
10/28/2004WO2004093086A2 Magnetically lined conductors
10/28/2004WO2004093085A2 Method and system for providing a magnetic memory having a wrapped write line
10/28/2004WO2004093083A2 Methods and apparatus for selectively updating memory cell arrays
10/28/2004WO2004092966A1 A virtual dual-port synchronous ram architecture
10/28/2004US20040216006 Semiconductor memory device capable of accessing all memory cells
10/28/2004US20040215912 Method and apparatus to establish, report and adjust system memory usage
10/28/2004US20040215903 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories
10/28/2004US20040214395 Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers
10/28/2004US20040214389 Semiconductor latches and SRAM devices
10/28/2004US20040214384 Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation
10/28/2004US20040214351 Polymer-based ferroelectric memory
10/28/2004US20040214116 Anisotropic ribbed structure, which allows it to be suitable for carriage in a roll form and allows for the rib to be utilized when viewing images printed on the media
10/28/2004US20040213613 Image sensing apparatus including a microcontroller
10/28/2004US20040213482 Method of capturing and processing sensed images
10/28/2004US20040213074 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
10/28/2004US20040213073 Data input unit of synchronous semiconductor memory device, and data input method using the same
10/28/2004US20040213069 Sram control circuit with a power saving function
10/28/2004US20040213064 Semiconductor memory device with common I/O type circuit configuration achieving write before sense operation
10/28/2004US20040213061 Semiconductor device with self refresh test mode
10/28/2004US20040213058 Semiconductor integrated circuit device having a test function
10/28/2004US20040213057 Memory device having redundant memory cell
10/28/2004US20040213056 Redundancy control circuit which surely programs program elements and semiconductor memory using the same
10/28/2004US20040213055 Magneto-resistive memory cell structures with improved selectivity
10/28/2004US20040213050 Semiconductor integrated circuit device
10/28/2004US20040213049 Novel multi-state memory
10/28/2004US20040213048 Nonvolatile memory having bit line discharge, and method of operation thereof
10/28/2004US20040213047 Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device
10/28/2004US20040213044 Hybrid MRAM array structure and operation
10/28/2004US20040213043 Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing
10/28/2004US20040213042 Magnetoelectronic device with variable magnetic write field
10/28/2004US20040213041 Magnetoelectronic memory element with inductively coupled write wires
10/28/2004US20040213040 Magnetic random access memory device
10/28/2004US20040213039 Magnetic ring unit and magnetic memory device
10/28/2004US20040213038 Ferroelectric memory device
10/28/2004US20040213037 Magnetoresistive memory and method for reading a magnetoresistive memory
10/28/2004US20040213036 Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
10/28/2004US20040213035 Sectored flash memory comprising means for controlling and for refreshing memory cells
10/28/2004US20040213034 Memory pumping circuit
10/28/2004US20040213033 Ferroelectric memory device
10/28/2004US20040213032 Ferroelectric memory device
10/28/2004US20040213031 Non-volatile semiconductor memory device and electric device with the same
10/28/2004US20040213029 Semiconductor memory and semiconductor integrated circuit
10/28/2004US20040213028 Read only memory (rom) and method for forming the same
10/28/2004US20040212933 Magnetoresistive device exhibiting small and stable bias fields independent of device size variation
10/28/2004US20040212652 Printing cartridge with pressure sensor array identification
10/28/2004US20040212576 Dynamic self-refresh display memory
10/28/2004US20040212413 DLL Circuit
10/28/2004US20040212407 Semiconductor integrated circuit having system bus divided in stages
10/28/2004US20040212406 Clock divider and clock dividing method for a DLL circuit
10/28/2004US20040212394 Hardening logic devices
10/28/2004US20040212388 High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments
10/28/2004US20040212014 Semiconductor integrated circuit, semiconductor non-volatile memory, memory card, and microcomputer
10/28/2004US20040212005 Twin eeprom memory transistors with subsurface stepped floating gates
10/28/2004US20040211997 Ferroelectric memory device and method for manufacturing the same
10/28/2004US20040211996 Magnetic memory elements using 360 degree walls
10/28/2004US20040211995 Magnetic random access memory including middle oxide layer and method of manufacturing the same
10/28/2004US20040211749 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
10/28/2004DE102004016323A1 Redundanzsteuerschaltung zum sicheren Programmieren von Programmelementen und Halbleiterspeicher zur Verwendung derselben Redundancy control circuit for safe programming of program elements and semiconductor memory for using the same
10/28/2004DE102004010838A1 Verfahren zum Bereitstellen von Adressinformation über ausgefallene Feldelemente und das Verfahren verwendende Schaltung A method for providing address information about failed field elements and the process circuit used
10/27/2004EP1471644A1 Logical operation circuit and logical operation method
10/27/2004EP1471643A1 Logical operation circuit and logical operation method
10/27/2004EP1471577A2 Byte-operational nonvolatile semiconductor memory device
10/27/2004EP1471543A2 Magnetoresistive structures and magnetic recording disc drive
10/27/2004EP1471536A2 Magnetic random access memory cell comprising an oxidation preventing layer and method of manufacturing the same
10/27/2004EP1471495A2 Dynamic self-refresh display memory
10/27/2004EP1470566A2 Emitter and method of making
10/27/2004EP1470553A1 Apparatus and method for encoding auto-precharge
10/27/2004CN1540766A Follower, digital memory module and SRAM
10/27/2004CN1540762A Flash memory possessing groove type selection grid and manufacturing method
10/27/2004CN1540760A Semiconductor storage and semiconductor integrated circuit
10/27/2004CN1540668A Non-volatile semiconductor memory
10/27/2004CN1540667A Electricity writing in and heat erasable organic electric bistable thin film, and applicaton
10/27/2004CN1540621A Dynamic self-refreshing display memorage
10/27/2004CN1540464A Electricity saving controlling circuit in electronic equipment and method for saving electricity