Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
01/2010
01/05/2010US7643335 Apparatus and systems using phase change memories
01/05/2010US7643334 High-speed controller for phase-change memory peripheral device
01/05/2010US7643333 Process for erasing chalcogenide variable resistance memory bits
01/05/2010US7643332 MRAM cell using multiple axes magnetization and method of operation
01/05/2010US7643331 Semiconductor device
01/05/2010US7643330 Sequentially-accessed 1R/1W double-pumped single port SRAM with shared decoder architecture
01/05/2010US7643329 Asymmetric four-transistor SRAM cell
01/05/2010US7643328 Method of writing into semiconductor memory device
01/05/2010US7643327 Driving a memory matrix of resistance hysteresis elements
01/05/2010US7643326 Semiconductor memory device with ferroelectric device
01/05/2010US7643325 Ferroelectric memory and operating method of same
01/05/2010US7642620 Semiconductor apparatus
01/05/2010US7642138 Split-channel antifuse array architecture
01/05/2010US7642098 Ferromagnetic or ferrimagnetic layer, method for the production thereof, and use thereof
01/05/2010US7641315 Printhead with reciprocating cantilevered thermal actuators
01/05/2010US7641314 Printhead micro-electromechanical nozzle arrangement with a motion-transmitting structure
12/2009
12/31/2009US20090323449 Circuit and method for controlling self-refresh cycle
12/31/2009US20090323448 Bias Sensing in Dram Sense Amplifiers Through Voltage-Coupling/Decoupling Device
12/31/2009US20090323437 Method and Apparatus for Data Inversion in Memory Device
12/31/2009US20090323416 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
12/31/2009US20090323414 Method and Device for Storing Data
12/31/2009US20090323411 Method including selective treatment of storage layer
12/31/2009US20090323410 System and Method to Fabricate Magnetic Random Access Memory
12/31/2009US20090323409 Methods for high speed reading operation of phase change memory and device employing same
12/31/2009US20090323408 Methods for determining resistance of phase change memory elements
12/31/2009US20090323407 Memory device, an information storage process, a process, and a structured material
12/31/2009US20090323406 Magnetic memory element, and method of manufacturing memory element
12/31/2009US20090323405 Controlled Value Reference Signal of Resistance Based Memory Circuit
12/31/2009US20090323404 Write Operation for Spin Transfer Torque Magnetoresistive Random Access Memory with Reduced Bit Cell Size
12/31/2009US20090323403 Spin-transfer torque memory non-destructive self-reference read method
12/31/2009US20090323402 Spin-transfer torque memory self-reference read method
12/31/2009US20090323401 8t low leakage sram cell
12/31/2009US20090323400 Semiconductor device
12/31/2009US20090323399 Semiconductor memory device
12/31/2009US20090323398 Semiconductor memory device comprising a plurality of static memory cells
12/31/2009US20090323397 Nonvolatile semiconductor memory device and reading method of nonvolatile semiconductor memory device
12/31/2009US20090323396 Semiconductor memory device
12/31/2009US20090323395 Semiconductor storage device
12/31/2009US20090323394 Pulse reset for non-volatile storage
12/31/2009US20090323393 Capacitive discharge method for writing to non-volatile memory
12/31/2009US20090323392 Smart detection circuit for writing to non-volatile storage
12/31/2009US20090323391 Reverse set with current limit for non-volatile storage
12/31/2009US20090323390 Semiconductor memory device
12/31/2009US20090323384 High density content addressable memory using phase change devices
12/31/2009US20090323383 Comparing data representations to stored patterns
12/31/2009DE19954564B4 Steuerungsschaltung für die CAS-Verzögerung Control circuit for the CAS latency
12/31/2009DE19839089B4 Datenpuffer für einen programmierbaren Speicher mit mehreren Zuständen Data buffer for a programmable memory multi-state
12/31/2009DE10214707B4 Auffrisch-Mechanismus in dynamischen Speichern Refresh mechanism in dynamic memories
12/31/2009DE10211337B4 Schaltkreis-Anordnung und Verfahren zum Betreiben einer Schaltkreis-Anordnung Circuit arrangement and method for operating a circuit arrangement
12/31/2009DE102008027392A1 Schaltung und Verfahren zum Betrieb einer Schaltung Circuit and method for operating a circuit
12/31/2009DE10165025B4 Halbleiterspeicherbauelement mit Subwortleitungstreibern The semiconductor memory device with Subwortleitungstreibern
12/31/2009DE10130752B4 Halbleiterspeichervorrichtung mit Schaltung zur Erzeugung eines verstärkten Potentials und zugehöriges Steuerverfahren A semiconductor memory device with circuitry for generating a boosted potential and associated control method
12/30/2009WO2009158274A1 Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size
12/30/2009WO2009158055A1 Spin-transfer torque memory non-destructive self-reference read method
12/30/2009WO2009157489A1 Semiconductor storage device sense amplification circuit
12/30/2009WO2009157101A1 Magnetic memory element and its driving method and nonvolatile memory device
12/30/2009WO2009157100A1 Spin valve recording element and storage device
12/30/2009WO2009156876A1 Fast, low-power reading of data in a flash memory
12/30/2009WO2009156869A1 Reading a flash memory by joint decoding and cell voltage distribution tracking
12/30/2009WO2009155638A1 Rfid memory devices
12/30/2009WO2009117228A3 Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors
12/30/2009WO2008131137A3 Programmable floating gate reference
12/30/2009EP2137734A1 Spin transfer torque magnetoresistive random access memory and design methods
12/30/2009EP1673782B1 Mram array with segmented word and bit lines
12/30/2009CN101617369A Memory having a dummy bitline for timing control
12/30/2009CN101615428A Detection method in non-volatile memory and reading method
12/30/2009CN101615426A A programmable conductor random access memory and a method for writing thereto
12/30/2009CN101615425A Phase change memory with dual word lines and source lines and method of operating same
12/30/2009CN101615424A 8t low leakage sram cell
12/30/2009CN101615423A Information storage devices and methods of operating the same
12/30/2009CN100576359C Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
12/30/2009CN100576358C Latched programming of memory and method
12/30/2009CN100576350C Nand flash memory device
12/30/2009CN100576349C Memory unit of static random access memory
12/30/2009CN100576348C Method and test device for determining a repair solution for a memory module
12/30/2009CN100576347C Semiconductor storage and its word line selection circuit
12/30/2009CN100576346C Information reading apparatus, method and corresponding storage medium
12/30/2009CN100576345C Magnetic memory architecture with shared current line
12/30/2009CN100576344C Synthetic-ferrimagnet sense-layer for high density MRAM applications
12/30/2009CN100576343C Antiferromagnetically stabilized pseudo spin valve for memory applications
12/30/2009CN100576340C DRAM stacked package, DIMM, and semiconductor manufacturing method
12/30/2009CA2726471A1 Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size
12/29/2009US7640413 Detection circuit for mixed asynchronous and synchronous memory operation
12/29/2009US7640391 Integrated circuit random access memory capable of automatic internal refresh of memory array
12/29/2009US7639771 Memory device with external magnetic field generator and method of operating and manufacturing the same
12/29/2009US7639549 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
12/29/2009US7639544 Non-volatile semiconductor memory
12/29/2009US7639543 High speed cascode circuit with low power consumption
12/29/2009US7639542 Maintenance operations for multi-level data storage cells
12/29/2009US7639541 Semiconductor device
12/29/2009US7639537 Method for writing data in a non volatile memory unit
12/29/2009US7639535 Detection and correction of defects in semiconductor memories
12/29/2009US7639533 Multi-level memory cell programming methods
12/29/2009US7639531 Dynamic cell bit resolution
12/29/2009US7639530 Method for programming and erasing an NROM cell
12/29/2009US7639528 Nanocrystal write once read only memory for archival storage
12/29/2009US7639527 Phase change memory dynamic resistance test and manufacturing methods
12/29/2009US7639526 Method for multilevel programming of phase change memory cells using a percolation algorithm
12/29/2009US7639525 Semiconductor memory device
12/29/2009US7639524 Multi-bit nonvolatile memory devices and methods of operating the same
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